Tsung-Yu Yang

Low-Loss and Broadband Asymmetric Broadside-Coupled Balun for Mixer Design in 0.18-

This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature asymmetric broadside coupled Marchand baluns are implemented to demonstrate the applicability to MOS technology. Both a single and dual balun occupy an area of only 0.06 mm2. The balun achieves a measured bandwidth of over 120%, an insertion loss of better than 4.1 dB (3 dB for an ideal balun) at the center frequency, an amplitude imbalance of less than 1 dB, and a phase imbalance of less than 5deg from 10 to 60 GHz. The first demonstrated circuit is a Ku-band mixer, which is implemented with a miniaturized balun to reduce the chip area by 80%. This 17-GHz mixer yields a conversion loss of better than 6.8 dB with a chip size of 0.24 mm2. The second circuit is a 15-60-GHz broadband single-balanced mixer, which achieves a conversion loss of better than 15 dB and occupies a chip area of 0.24 mm2. A three-conductor miniaturized dual balun is then developed for use in the third mixer. This star mixer incorporates two miniature dual baluns to achieve a conversion loss of better than 15 dB from 27 to 54 GHz, and occupies a chip area of 0.34 mm2.

\mu{\hbox {m}}

A 25-75 GHz compact double balanced frequency doubler fabricated in standard 0.18-mum CMOS process is demonstrated. The resistive doubler is composed of two identical asymmetric broadside-coupled baluns, and a quad GS-connected diode. The fabricated doubler achieves a radio frequency bandwidth from 25 to 75 GHz with a maximum output power better than +3 dBm; the fundamental signal rejection is ranging from 32 to 59 dB, and only occupies a chip size of 0.24 mm2. To the knowledge of the authors, this double balanced frequency doubler is the first demonstration with an operating frequency up to 75 GHz in 0.18-mum CMOS technology and shows this silicon-based frequency doubler can compare with its GaAs counterpart.

CMOS Technology

This work presents a miniature Q-band balanced single side-band sub-harmonically pumped image rejection diode mixer (SHIRM) using a compact Marchand dual balun design. The SHIRM is realized employing four anti-parallel diode pairs for frequency mixing, a Lange coupler for radio frequency (RF) signal input, and a reduced size three-conductor-line Marchand dual balun for local oscillator pumping. The length of three-conductor-line dual balun is reduced by 81% after shunting two lumped capacitors at the center conductor. The measured results exhibit a minimum conversion loss of 8.6 dB, a maximum image rejection ratio of 22 dB, all ports isolation better than 37 dB, and an input 1-dB compression point of 2.5 dBm at RF bandwidth of 40.5 to 43.5 GHz and fixed intermediate frequency of 2.4 GHz. The chip area is very compact, only 1 times 0.84mm2

A 25–75 GHz Miniature Double Balanced Frequency Doubler in 0.18-

A compact V-band star monolithic microwave integrated circuit mixer has been designed using compensated overlay capacitors in dual baluns for the input of local oscillator and radio frequency ports. The reduced-size balun can be simply realized by shunting overlay capacitor in either input or end of balun. The proposed V-band star mixer achieved a conversion loss of 8.6 dB, the port-to-port isolations better than 18 dB, and an input 1-dB compression point higher than 7.7 dBm at 60 GHz. Moreover, better than 50% length reduction of dual balun was achieved, and chip size of star mixer including pads was less than 0.68 times 0.59 mm2.

\mu

A 16-46 GHz mixer using broadband balun fabricated in standard 0.18-mum CMOS process is demonstrated. The broadside-coupled balun with wide bandwidth and low insertion loss utilizes the inherent 3D multilayer structure in CMOS process. The mixer exhibits radio frequency bandwidth from 16 to 46 GHz with a conversion loss ranging from 13 plusmn 1.5 dB, and achieves bandwidth over 103% with a compact chip size of 0.24 mm2.

m CMOS Technology

A 5.8GHz low voltage, high linear and isolation transformer based mixer using 0.18mum CMOS process for WLAN receiver was investigated. The proposed fully integrated transformer featured that biasing, coupling, and filtering functions in an RF input stage commutated the input RF voltage to current, which was coupled to local oscillator (LO) switching pairs. This implementation excluded the current source transistor at bottom and furthermore reduced the supply voltage. The designed mixer required only a 0.8V supply voltage and consumed less than 10mW DC power. A high third-order intercept point of +3dBm and an input second-order intercept point of +19dBm had been achieved. The excellent LO/RF and RF/IF isolations were achieved up to 54dB and 74dB, respectively

A Miniature

The VCO using differential-driven inductor obtains better performances in many folds such as phase noise, area-saving and higher harmonic rejection. Two VCOs are implemented using 0.35-/spl mu/m CMOS technology with 25-GHz-f/sub t/, 30-GHz-f/sub max/. The figure of merit (FOM) of VCO using differential-driven inductor is eight higher than using single-excited inductor and saving chip area around 50% (without including pads). The VCO with single-ended inductor achieves 320MHz tuning range with -4.5 dBm output power and phase noise about -102dBc/Hz at 1MHz offset frequency. The VCO with differential-driven inductor achieves 210MHz tuning range with -6.8 dBm output power and phase noise about -112dBc/Hz at 1MHz offset frequency. The core current of these VCOs is 8mA at 2.4-V supply voltage.

Q

A high efficiency SiGe HBT differential power amplifier with an open collector adaptive bias was successfully demonstrated. A novel linearizer consists of an open collector heterojunction bipolar transistor bias circuit and an MOS feedback diode was proposed, which achieved better power added efficiency (PAE) than that of traditional adaptive bias circuits. The size effect of linearizer was investigated and the impedance ratio (R 1 /R 2 ) between the linearizer and the main amplifier was optimized by the factor of 3. The measured differential power amplifier achieved an output 1-dB compression point (P 1 dB ) of 18.7 dBm with PAE of 31.2%, the output second order intermodulation point (OIP 2 ) of 59 dBm, and third-order intermodulation point (OIP 3 ) of 28 dBm. Compared to traditional adaptive bias technique, the proposed linearizer power amplifier effectively improved the PAE. The fabricated die size including pads is less than 0.925 mm 2 and suitable for highly integrated linear drive amplifier.

-Band Balanced Sub-Harmonically Pumped Image Rejection Mixer

Ruthroff-type transmission line transformers (TLTs) and baluns prevail over their broadband and low-loss performance. A typical Ruthroff-type balun with a 1:4 step-up impedance transformation ratio was successfully presented using integrated passive devices (IPDs) process. Moreover, two proposed baluns with step-down impedance transformation ratios of 1:1 and 9:4 were developed by modifying the combination of one Ruthroff-type TLT and one Ruthroff-type balun. The two proposed impedance step-down baluns whose balanced impedance is lower than unbalanced impedance make Ruthroff-type balun more flexible for applications; meanwhile, fabricating the baluns using IPD process can help to enhance the low-loss performance. The measured results show that the proposed 1:1 balun exhibits an insertion loss of 0.46 dB with 1-dB fractional bandwidth of 138.9%, and the proposed 9:4 balun exhibits an insertion loss of 0.75 dB with 1-dB fractional bandwidth of 72.4%. The chip areas of the proposed 1:1 and 9:4 baluns, including the pads, are 0.6 and 0.64 mm2, respectively. The two proposed baluns are the first on-chip step-down Ruthroff-type baluns and having an option of center tap, which is highly contributive to wideband and high-efficiency power amplifier design.

A Compact V-Band Star Mixer Using Compensated Overlay Capacitors in Dual Baluns

This work reports a compact monolithic sub-harmonically pumped resistive mixer (SPRM) with miniature hybrid elements which include a capacitive compensation balun and a reduced size power divider. This MMIC mixer was fabricated by using Win-semiconductors 0.15/spl mu/m GaAs pHEMT technology. The proposed power divider utilizes a combination of shorted coupled lines instead of lumped inductors and capacitors. The traditional the length of Marchand balun are significantly reduced by shunted capacitors. The balun and divider are then applied in the design of a 28-GHz monolithic SPRM. As a result the dice area of SPRM only occupies 1.5mm/sup 2/. The measured conversion loss of the mixer is less than 13 dB at an RF bandwidth of 27.5-28.5 GHz at 1 GHz fixed IF frequency, over 35 dB of LO-RF isolation, and a 9 dBm of 1-dB compression point.