Kuei-Cheng Lin

A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver

A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP3 ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolations of better than 50 dB. The input second-order (IIP 2) and IIP 3 are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are then integrated with a differential low-noise amplifier (DLNA) and a poly-phase filter, to from a direct-conversion receiver (DCR). The DCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mW power consumption from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP2 and the IIP3 of the DCR are 33 dBm and -12 dBm, respectively.

2.4-GHz Complementary Metal Oxide Semiconductor Power Amplifier Using High-Quality Factor Wafer-Level Bondwire Spiral Inductor

A complementary metal oxide semiconductor (CMOS) power amplifier (PA) using a wafer-level bondwire spiral inductor with high-quality factor (Q) is presented. The inductor is made by three top metal traces connected with bondwire loops above the CMOS chip. The proposed inductor with 2.75-nH inductance achieves a Q of 18, which is three times as much as that of a conventional CMOS standard spiral inductor at 2.4 GHz. The Q of the inductor is over 15 from 2 to 14 GHz, which can cover the frequency band of wireless sensor network and worldwide interoperability for microwave access applications. The output power and power-added efficiency of the PA with the inductor are improved by 1.5 dBm and 7% as compared with those of the fully integrated CMOS PA, respectively.

High Efficiency Open Collector Adaptive Bias SiGe HBT Differential Power Amplifier

A high efficiency SiGe HBT differential power amplifier with an open collector adaptive bias was successfully demonstrated. A novel linearizer consists of an open collector heterojunction bipolar transistor bias circuit and an MOS feedback diode was proposed, which achieved better power added efficiency (PAE) than that of traditional adaptive bias circuits. The size effect of linearizer was investigated and the impedance ratio (R 1 /R 2 ) between the linearizer and the main amplifier was optimized by the factor of 3. The measured differential power amplifier achieved an output 1-dB compression point (P 1 dB ) of 18.7 dBm with PAE of 31.2%, the output second order intermodulation point (OIP 2 ) of 59 dBm, and third-order intermodulation point (OIP 3 ) of 28 dBm. Compared to traditional adaptive bias technique, the proposed linearizer power amplifier effectively improved the PAE. The fabricated die size including pads is less than 0.925 mm 2 and suitable for highly integrated linear drive amplifier.

Variable gain active predistorter with linearity enhancement for a 2.4 GHz SiGe HBT power amplifier design

This paper proposes a 2.4 GHz SiGe HBT differential power amplifier (PA) with a novel on-chip variable gain active predistorter (PD) for linearity enhancement. The fully differential active PD provides an open collector adaptive bias control which can effectively enhance the linearity while improve power added efficiency (PAE). The PA with active PD achieves an output 1-dB compression (OP1dB) of 20 dBm, a gain control range of 10 dB, a PAE of 30%, and an error vector magnitude (EVM) improvement of 2.4 % under OFDM/64-QAM modulation signal. The fabricated die size including pads is less than 0.74 mm2 and suitable for highly integrated linear PA.

A 1.8-V monolithic SiGe HBT power amplifier with a novel proposed linearizing bias circuit

In this work, we report a linearization technique by using an on-chip linearizer. The linearizer consists of a SiGe heterojunction bipolar transistors active bias circuit with a MOSFET feedback junction capacitor, which significantly improves the gain compression and phase distortion without additional dc consumption. The proposed circuit topology finds extensive applications in high efficiency and linearity power amplifier design. The power amplifier is implemented by using TSMC 0.18 mum SiGe HBT technology. The compact VBIC model of SiGe HBT was successfully established for the circuit design, and then a 2 GHz power amplifier was designed for demonstrating the circuit performances. The HBT power amplifier exhibits an output power over 20 dBm with a power-added efficiency higher than 42.4% under 1.8 volt operation

5-GHz SiGe linearity power amplifier using integrated feedforward architecture for WLAN applications

This work presents a 5-GHz power amplifier (PA) based on a tsmc™ 0.35-μm SiGe heterojunction bipolar transistor (HBT) process. The PA adopts an on-chip linearizer as a feedforward element that cancels third-order distortion at the PA output. The PA achieves an output 1-dB compression point (OP1dB) of 27 dBm, a power gain of 21.9 dB, and a power added efficiency of 31 %. Compared to a PA without a linearizer, the proposed PA improves the third-order distortion by 12 dB. For an OFDM/64-QAM signal, the error vector magnitude is minimized to 1.5 % at an output power of 18 dBm. The fabricated chip size is 2.17 mm2 and is suitable for use in a highly integrated PA.

A 28 dBm P out 5-GHz CMOS power amplifier using integrated passive device power combining transformer

This work presents a 5-GHz power amplifier (PA) based on a tsmc 0.18-μm CMOS process. A high quality factor (Q) transformer for use by the PA was fabricated using wafer-level integrated passive device (IPD) technology and stacked on top of the active region of the CMOS PA chip. PAs with and without the IPD transformer were designed and their performance was compared. For a 1.8-V supply voltage, the IPD CMOS-PA achieved an output power of 28 dBm and power added efficiency (PAE) of 25%; these were, respectively, 1.3 dBm and 6% higher than the corresponding output parameters of the typical CMOS PA at the same power consumption. In sending OFDM/64-QAM modulated signals, the IPD CMOS-PA produced a measured adjacent channel power radio (ACPR) and error vector magnitude (EVM) of -43 dBc and 1.6%, respectively.