Hyeonuk Son

Multi-operation-based Constrained Random Verification for On-Chip Memory

Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors.

A New Analog-to-Digital Converter BIST Considering a Transient Zone

A new BIST (Built-in Self-test) method for static ADC testing is proposed. The proposed method detects offset, gain, INL (Integral Non-linearity) and DNL (Differential Non-linearity) errors with a low hardware overhead. Moreover, it can solve a transient zone problem which is derived from the ADC noise in real test environments.

A low-cost DDEM ADC structure for the testing of high-performance DACs

The testing of high resolution and high speed DACs (Digital-to-Analog Converters) is extremely challenging because of the requirements on the accuracy, speed and cost. This paper presents a new hardware overhead reduction method using DDEM (Deterministic Dynamic Element Matching) techniques for the testing of DACs. In this work, the proposed method make that resistors in a resistor string have different lengths by a merging operation. Accuracy of the proposed method is proven by theoretical analysis. The experimental results show that the proposed method reduces the usage of resources over 17%.

A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters

SUMMARY In this letter a histogram-based BIST (Built-In Self-Test) approach for deriving the main characteristic parameters of an ADC (Analog to Digital Converter) such as offset, gain and non-linearities is proposed. The BIST uses a ramp signal as an input signal and two counters as a response analyzer to calculate the derived static parameters. Experimental results show that the proposed method reduces the hardware overhead and testing time while detecting any static faults in an ADC.

Histogram-Based Calibration Method for Pipeline ADCs

Measurement and calibration of an analog-to-digital converter (ADC) using a histogram-based method requires a large volume of data and a long test duration, especially for a high resolution ADC. A fast and accurate calibration method for pipelined ADCs is proposed in this research. The proposed calibration method composes histograms through the outputs of each stage and calculates error sources. The digitized outputs of a stage are influenced directly by the operation of the prior stage, so the results of the histogram provide the information of errors in the prior stage. The composed histograms reduce the required samples and thus calibration time being implemented by simple modules. For 14-bit resolution pipelined ADC, the measured maximum integral non-linearity (INL) is improved from 6.78 to 0.52 LSB, and the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are improved from 67.0 to 106.2dB and from 65.6 to 84.8dB, respectively.

Reduced-code test method using sub-histograms for pipelined ADCs

The measurement of static test parameters for an analog-todigital converter (ADC) requires a large volume of test data, especially for a high-resolution ADC. This paper proposes a reduced-code test method for pipelined ADCs that does not compromise test accuracy. The proposed method calculates fault information at each stage by using sub-histograms. The simulation results based on 12-bit pipelined ADCs show a maximum integral nonlinearity error of 0.590 LSB with only 3.92% of the codes required for the conventional histogram-based method.

A new static test of a DAC with a built-in structure

A new BIST (Built-In Self-Test) scheme to test static parameters of a DAC (Digital-to-Analog Converter) is proposed in this paper. The proposed BIST employs a ramp generator and two voltage references to calculate static parameters of a DAC such as offset, gain, INL (Integral Non-Linearity) and DNL(Differential Non-Linearity). The optimization of calculating static parameters and the element sharing can reduce the BIST circuitry. The simulation results which validate our method are able to detect the linearity errors with the simple hardware architecture.