Kicheol Kim

Code-width testing-based compact ADC BIST circuit

This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.

A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals

Testing PLLs (phase-locked loops) is becoming an important issue that affects both time-to-market and production cost of electronic systems. Though a PLL is the most common mixed-signal building block, it is very difficult to test due to internal analog blocks and signals. In this paper, we propose a new PLL BIST (built-in self test) using the distorted frequency detector that uses only internal digital signals. The proposed BIST does not need to load any analog nodes of the PLL. Therefore, it provides an efficient defect-oriented structural test scheme, reduced area overhead, and improved test quality compared with previous approaches.

A New Analog-to-Digital Converter BIST Considering a Transient Zone

A new BIST (Built-in Self-test) method for static ADC testing is proposed. The proposed method detects offset, gain, INL (Integral Non-linearity) and DNL (Differential Non-linearity) errors with a low hardware overhead. Moreover, it can solve a transient zone problem which is derived from the ADC noise in real test environments.

A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters

SUMMARY In this letter a histogram-based BIST (Built-In Self-Test) approach for deriving the main characteristic parameters of an ADC (Analog to Digital Converter) such as offset, gain and non-linearities is proposed. The BIST uses a ramp signal as an input signal and two counters as a response analyzer to calculate the derived static parameters. Experimental results show that the proposed method reduces the hardware overhead and testing time while detecting any static faults in an ADC.

TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure

Power of scan operation is dominant factor. This paper proposed the structure to reduce scan power totally. The total scan power reduction architecture uses a duplicated transition monitoring window and sub-scan chains. Experimental results show 60% transition reduction, 2-4% fault coverage improvement, and 25% scan-in and 26% scan-out transition by the TOSCA

A New Low Power Test Pattern Generator for BIST Architecture

A new low power test pattern generator (TPG) which can effectively reduce the average power consumption during test application is developed. The new TPG reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at some primary inputs which make many transitions. Moreover, the new TPG does not lose fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 33.8% while achieving high fault coverage.