Hyosang Kang

Pulsed CVD-W Nucleation Layer Using WF6 and B2H6 for Low Resistivity W

Tungsten (W) thin films were deposited using the modified chemical vapor deposition (CVD), the so-called pulsed CVD, and their properties were characterized as nucleation layers for the chemical vapor deposited W (CVD-W) technology of sub-50 nm memory devices. W growth per cycle was extremely linear with a higher growth rate of ∼0.58 nm/cycle as compared to that (∼0.28 nm/cycle) of the atomic layer deposition (ALD) process using the same chemistry. From the X-ray diffractometry, the pulsed CVD-W film was formed as an amorphous structure, which was the same as the atomic layer deposited W. This led to the formation of a low resistivity bulk CVD-W film deposited on it with the grain size of ∼ 180 nm at 200 nm thick film, and its resistivity was further decreased with the B 2 H 6 post-treatment before the deposition of bulk CVD-W film (∼ 13 μΩ cm at a 50 nm thick film). However, we found that the adhesion performances of CVD-W growing on the B 2 H 6 -based pulsed CVD-W nucleation layer were significantly degraded as both the deposition temperature of the nucleation layer and the B 2 H 6 post-treatment time increased. High resolution transmission electron microscopy and energy-dispersive spectroscopy analysis clearly demonstrated that a discontinuous boron layer was formed at the bulk CVD-W/nucleation layer interface, which was dominantly due to the B 2 H 6 decomposition during the B 2 H 6 post-treatment. We strongly suggest that a boron-containing discontinuous layer degrades the adhesion properties of CVD-W films growing on it. Considering the thermodynamics of the B 2 H 6 decomposition, we can improve the adhesion properties by increasing the H 2 flow rate at the post-treatment step.

Improvement of Adhesion Performances of CVD-W Films Deposited on B2H6-Based ALD-W Nucleation Layer

The resistivity of chemical-vapor-deposited (CVD)-W film was reported to be significantly reduced using a B 2 H 6 -based atomic layer deposited (ALD)-W nucleation layer for continuously shrinking memory devices. But, we found that the adhesion performances of CVD-W films growing on the B 2 H 6 -based ALD-W nucleation layer were poor compared to those on the SiH 4 -based W nucleation layer. Scanning electron microscopy and secondary ion mass spectrometry analysis clearly suggest that the boron penetration into the interface between underlying TiN and SiO 2 during the deposition of W nucleation layer is a possible reason to degrade the adhesion performances of CVD-W films with B 2 H 6 -based W nucleation layers. By rigorous selection of both the deposition conditions for W nucleation layer and diffusion barrier materials, we can demonstrate the successful deposition of CVD-W film with a very low resistivity of ∼12 μΩ cm (50 nm in thickness) without an adhesion failure. Noticeably, the application of 5 nm thick sputter-deposited WN x film as a glue layer was found to present an excellent adhesion performance, which was due to its excellent diffusion barrier performance with amorphous structure.

Comparison study for 3x-nm contact hole CD uniformity between EUV lithography and ArF immersion double patterning

In order to continue scaling down the feature sizes of the devices, EUV lithography is regarded as the most powerful candidate for patterning. So It has being studied to overcome the several issues such as source power for high throughput to apply volume production, mask defectivity from mask blank, RLS (Resolution, LWR & Sensitivity) trade off, which is the intrinsic property of EUV resist, and so on. For 2x nm node DRAM, dense contact hole, which has 3x nm half pitch (hp), has been issued to be made so far. There are two well-known methods for pattering; hole double patterning with ArF immersion lithography and single patterning with EUV lithography. EUV is more simple solution than hole double patterning for 3xnm hp dense contact hole, if it has large process window and comparable CD uniformity. Fortunately, EUV process already has larger process window than that of ArF immersion because its k1 value is a little bit high. But CD (critical dimension) uniformity and pattern profile were very poor in our initial result. Therefore it needs a lot of efforts to improve and compete against double patterning. The double patterning performance for 3xnm hp contact hole has been shown last year. In this paper, we will investigate on improving CD uniformity and pattern profile for 3x nm hp contact hole with several methods. Finally, the performance of EUV, which is achieved by our experiments, is being compared with that of double patterning in terms of CD uniformity and pattern profile.

EUV mask defect analysis from mask to wafer printing

ASML NXE3100 has been introduced for EUV Pre-Production, and ASML NXE3300 for High Volume Manufacturing will be installed from this year. EUV mask defect control is the one of the concerns for introducing EUVL to device manufacturing, for current EUV mask defect level is too high to accept for device volume production. EUV mask defects come from mask blank, mask process and mask handling. To have reduced mask defect level, quality control of blank mask, optimization of EUV mask process and improvement of EUV mask handling need to be ready. In this paper, we analyze printed defects exposed from EUV full field mask at NXE3100. For this analysis we trace mask defects from mask to wafer printing. From this we will show current EUV mask’s defect type and numbers. Acceptable defect type, size and numbers for device manufacturing with EUVL will be shown. Through investigating printing result of natural ML defects, realistic level of natural ML defects will be shown.

A scatterometry-based CD uniformity control solution for Spacer Patterning Technology

Improving Critical Dimension Uniformity (CDU) for spacer double patterning features is a high priority for double patterning technology. In spacer double patterning the gaps between the spacers are established through various processes (litho, etch, deposition) with different process fingerprints and the CDU improvement of these gaps requires an improved control solution. Such a control solution is built upon two pillars: metrology and a control strategy. In this paper Spacer Patterning Technology CDU control using an angle resolved scatterometry tool is evaluated. CD results obtained with this scatterometer on CDU wafers are measured and the results are correlated with those from the traditional CD-SEM. CD wafer fingerprints are compared before and after applying the advanced control strategy and CDU improvements are reported. Based on the results it is concluded that scatterometry qualifies for a spacer process CDU control loop in a manufacturing environment.

The study and simulation of high-order overlay control including field-by-field methodologies

Overlay continues to be one of the key challenges for photolithography in semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. The corresponding tighter overlay specs require the consideration of new paradigms for overlay control, such as high-order control schemes and/or field-by-field overlay control. These approaches have been demonstrated to provide tighter overlay control for design rule structures, and can be applied to areas such as double patterning lithography (DPL), as well as for correcting non-linear overlay deformation signatures caused by non-lithographic wafer processing. Previously we presented a study of high-order control applied to high order scanner correction, high order scanner alignment, and the sampling required to support these techniques. Here we extend this work, using sources of variation (SOV) techniques, and have further studied the impact of field by field compensation. This report will show an optimized procedure for high order control using production wafers and field by field control.

Study on CD variation in the vicinity of the exposure field edge in EUV lithography

Intra-field CD uniformity control is one of hurdles in EUV lithography. Reflection imaging system intrinsic to EUV causes CD non-uniformity especially in exposure field edge. To analyze dominant contributors to make this intra-field CD non-uniformity in EUV lithography, influence of flare from adjacent fields and in-band and out of band refection from reticle masking blind(REMA) and mask black border were investigated through intensive sampling of CD measurement. Also mask border condition and REMA open settings are split into various settings to find out the impacts from each contributor. Two ASML EUV scanners, alpha demo tool(ADT) and pre-production tool(PPT) are used for the experiment. Fortunately, DUV out of band(OoB), reflection of REMA and the flare from adjacent fields are found to be not significant in NXE3100. The results presented here lead us to the conclusion that the EUV refection from mask black border is the main contributor and CD non-uniformity of the field edge can be overcome through optimized REMA setting.

Mask registration and wafer overlay

Overlay continues to be one of the key challenges for lithography in advanced semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. Some low k1 techniques, such as Double Exposure and Double Patterning also add additional loss of the overlay margin due to the fact that the single layer pattern is created based on more than 1 exposure. Therefore, the overlay between 2 exposures requires very tight overlay specification. Mask registration is one of the major contributors to wafer overlay, especially field related overlay. We investigated mask registration and wafer overlay by co-analyzing the mask data and the wafer overlay data. To achieve the accurate cohesive results, we introduced the combined metrology mark which can be used for both mask registration measurement as well as for wafer overlay measurement. Coincidence of both metrology marks make it possible to subtract mask signature from wafer overlay without compromising the accuracy due to the physical distance between measurement marks, if we use 2 different marks for both metrologies. Therefore, it is possible to extract pure scanner related signatures, and to analyze the scanner related signatures in details to in order to enable root cause analysis and ultimately drive higher wafer yield. We determined the exact mask registration error in order to decompose wafer overlay into mask, scanner, process and metrology. We also studied the impact of pellicle mounting by comparison of mask registration measurement pre-pellicle mounting and post-pellicle mounting in this investigation.

Electrical performances of low resistive W buried gate using B 2 H 6 -reduced W nucleation layer technology for 30nm-based DRAM devices

Low resistive tungsten (W) interconnects using chemical vapor deposited W (CVD-W) films deposited on B2H6-reduced W nucleation layers have been successfully developed for the buried gate electrode of sub-30nm dynamic random access memory (DRAM). The low resistive W film showed excellent gap fill performance and larger grain size than that of the conventional CVD-W film at the 30nm shallow trench pattern. The gate resistance of low resistive W film was ∼25% reduced even at the 30nm trench pattern, which is due to the larger grain at the shallow trench. In addition, the gate oxide integrity and reliability were drastically improved, compared to the conventional CVD-W buried gate. However, the properties of transistor including saturation threshold voltage (Vtsat) and saturation drain current (Idsat) were degraded due to the penetration of boron into channel at the B2H6-reduced W nucleation layer. In order to adjust the transistor characteristics, the optimization of channel implantation condition is suggested.

How can we improve sub 40 nm Transistor properties by using Ion implantation

To extend current process, it is required develop new implantation method. One of promising candidates are carbon implant, cold implant, or cold carbon implantation. To improve transistor properties, we have evaluated those implantation methods in Lightly doped drain (LDD), Source/Drain(S/D,P+ BF2, N+ As) and N+ add implant step. Carbon (C+) implantation could improve Short channel effect(SCE), cold implantation decrease Drain induced barrier lowering(DIBL), Sense and amplifer(S/A) mismatch and contact resistance. Cold carbon implant improved junction Breakdown voltage(BV). Optimization of process conditions and junction profiles is required for optimum device performance.