Sunyoung Koo

Issues and challenges of double patterning lithography in DRAM

Double patterning lithography has been one of the candidates for sub-40nm patterning era, and has a lot of process issues to be confirmed. Last year, we presented the issues in double patterning lithography with a real flash gate pattern. Process flow was suggested and CD uniformity due to overlay was analyzed. And the layout decomposition and the two types of double patterning of positive and negative tone were studied with 1-dimensional pattern. In this paper, the implementation to DRAM patterns is examined, which consist of 2-dimensional patterns. Double patterning methods and the selection of their tone for each layer are studied, and the difficulties from the randomness of core pattern are also considered. As a result, DRAM patterns have more restrictions on the double patterning method and selection of tone, and the aggressive layout decomposition should be designed to solve the difficulty in core patterning. Therefore, 37nm DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles.

EUV stochastic noise analysis and LCDU mitigation by etching on dense contact-hole array patterns

Experimental local CD uniformity (LCDU) of the dense contact-hole (CH) array pattern is statistically decomposed into stochastic noise, mask component, and metrology factor. Each component are compared quantitatively, and traced after etching to find how much improvement can be achieved by smoothing. Etch CDU gain factor is defined as the differential of etch CD by resist CD, and used to estimate etch CDU on resist CDU. Stochastic noise has influenced on not only LCDU but also local placement error (LPE) of each contact-hole. This LPE is also decomposed into its constituents in the same statistical way. As a result, stochastic noise is found to be the most dominant factor on LCDU and LPE. Etch LCDU is well expected by Etch Gain factor, but LPE seems to be kept same after etching. Fingerprints are derived from the repeating component and the boundary size for excluding proximity effect in analysis is investigated.

Comparison study for 3x-nm contact hole CD uniformity between EUV lithography and ArF immersion double patterning

In order to continue scaling down the feature sizes of the devices, EUV lithography is regarded as the most powerful candidate for patterning. So It has being studied to overcome the several issues such as source power for high throughput to apply volume production, mask defectivity from mask blank, RLS (Resolution, LWR & Sensitivity) trade off, which is the intrinsic property of EUV resist, and so on. For 2x nm node DRAM, dense contact hole, which has 3x nm half pitch (hp), has been issued to be made so far. There are two well-known methods for pattering; hole double patterning with ArF immersion lithography and single patterning with EUV lithography. EUV is more simple solution than hole double patterning for 3xnm hp dense contact hole, if it has large process window and comparable CD uniformity. Fortunately, EUV process already has larger process window than that of ArF immersion because its k1 value is a little bit high. But CD (critical dimension) uniformity and pattern profile were very poor in our initial result. Therefore it needs a lot of efforts to improve and compete against double patterning. The double patterning performance for 3xnm hp contact hole has been shown last year. In this paper, we will investigate on improving CD uniformity and pattern profile for 3x nm hp contact hole with several methods. Finally, the performance of EUV, which is achieved by our experiments, is being compared with that of double patterning in terms of CD uniformity and pattern profile.

Comparative Study of Binary Intensity Mask and Attenuated Phase Shift Mask using Hyper-NA Immersion Lithography for Sub-45nm Era

In this paper, we will present comparison of attenuated phase shift mask and binary intensity mask at hyper-NA immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for polarized illumination in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of binary intensity mask are used for this experiment; those are ArF att.PSM ( MoSi:Å ), thick Cr ( 1030Å ) BIM (Binary Intensity Mask), thin Cr ( 590Å ) BIM and multi layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA immersion scanner are performed to study influence of mask structure, process margin and effect of polarization. Two types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with contact hole shape. Line and space pattern is also studied through 38nm to 50nm half pitch for this experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE is also used in order to study the influence of mask structure and polarization effect through rigorous EMF simulation. Transmission and polarization effects of zero and first diffraction order are simulated for both att.PSM and BIM. First and zero diffraction order polarization are shown to be influenced by the structure of masking film. As pattern size on mask decreases to the level of exposure wavelength, incident light will interact with mask pattern, and then transmittance changes for mask structure. Optimum mask bias is one of the important factors for lithographic performance. In the case of att.PSM, negative bias shows higher image contrast than positive one, but in case of binary intensity mask, positive bias shows better performance than negative one. This is caused by balance of amplitude between first diffraction order and zero diffraction order light. Process windows and mask error enhancement factors are measured with respect to various design rules, i.e., different k1 levels at fixed NA. In the case of one dimensional line and space pattern, thick Cr BIM shows the best performance through various pitches. But in case of two dimensional DRAM cell pattern, it is difficult to find out the advantage of BIM for sub-45nm. It needs further study for two dimensional patterns. Finally, it was observed that thick Cr binary intensity mask for sub-45nm has advantage for one dimensional line and space pattern.

Feasibility of EUVL thin absorber mask for minimization of mask shadowing effect

Conventional EVUL mask has 80nm absorber height which brings considerable shadowing effect. H-V CD bias of 40nm line and space by shadowing effect is more than 4nm, and that is expected to increase much more for narrower patterns by simulation. However various reports have been presented on mask shadowing bias correction, experimental results are not reliable to derive required mask bias correctly. Even more difficulty will arise when complex 2D structures are taken into account. Therefore minimization of shadowing effect by reducing absorber thickness is desirable. To transfer EUV lithography from experimental stage to HVM era, we need to find optimum absorber height of EUVL mask which allows us less shadowing effect with minimum loss of process window. In this paper, we present optimal absorber height of EUV mask which has been found in terms of shadowing effect and process window by simulation and exposure. To find minimized absorber height experimentally, we will compare the printing result of conventional and thin mask stack using simple 1:1 line and space and island patterns. Simulated H-V CD bias and process window will be presented.

Comparative study of DRAM cell patterning between ArF immersion and EUV lithography

In this paper, we will present comparison of DRAM cell patterning between ArF immersion and EUV lithography which will be the main stream of DRAM lithography. Assuming that the limit of ArF immersion single patterning is around 40nm half pitch, EUV technology is positioned on essential stage because development stage of device manufacturer is going down sub-40nm technology node. Currently lithography technology, in order to improve the limitation of ArF immersion lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been examined intensively. However, double patterning and spacer patterning technology are not cost-effective process because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. Therefore, lithography community is looking forward to improving maturity of EUVL technology. In order to overcome several issues on EUV technology, many studies are needed for device application. EUV technology is different characteristics with conventional optical lithography which are non-telecentricity and mask topography effect on printing performance. The printed feature of EUV is shifted and biased on the wafer because of oblique illumination of the mask. Consequently, target CD and pattern position are changed in accordance with pattern direction, pattern type and slit position of target pattern.1 For this study, we make sub-40nm DRAM mask for ArF immersion and EUV lithography. ArF attenuated PSM (Phase Shift Mask) and EUV mask (LTEM) are used for this experiment; those are made and developed by in-house captive maskshop. Simulation and experiment with 1.35NA ArF immersion scanner and 0.25NA EUV full field scanner are performed to characterize EUV lithography and to compare process margin of each DRAM cell. Two types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with contact hole shape. Line and space pattern is also studied through 24nm to 50nm half pitch for this experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE and Solid-EUV are also used in order to study characteristics of EUV patterning through rigorous EMF simulation. We also investigated shadowing effect according to pattern shape and design rule respectively. We find that vertical to horizontal bias is around 2nm on 32nm to 40nm half pitch line and space pattern. In the case of DRAM cell, we also find same result with line and space pattern. In view of mask-making consideration, we optimize absorber etch process. So we acquire vertical absorber profile and mask MTT(Mean To Target) within 10% of target CD through several pitch. Process windows and mask error enhancement factors are measured with respect to several DRAM cell pattern. In the case of one dimensional line and space and two dimensional brick wall pattern, vertical pattern shows the best performance through various pitches because of lower shadowing effect than horizontal pattern. But in case of contact hole DRAM cell pattern such as storage node pattern, it has bigger MEF value than one or two dimensional pattern because of independency of shadowing effect. Finally, we compare with 2x, 3x and 4x DRAM cell patterning performance in terms of pattern fidelity, slit CD uniformity and shadowing effect.

EUV mask particle adders during scanner exposure

As EUV reaches high volume manufacturing, scanner source power and reticle defectivity attract a lot of attention. Keeping a EUV mask clean after mask production is as essential as producing a clean EUV mask. Even though EUV pellicle is actively investigated, we might expose EUV masks without EUV pellicle for some time. To keep clean EUV mask under pellicle-less lithography, EUV scanner cleanliness needs to meet the requirement of high volume manufacturing. In this paper, we will show the cleanliness of EUV scanners in view of mask particle adders during scanner exposure. From this we will find several tendencies of mask particle adders depending on mask environment in scanner. Further we can categorize mask particle adders, which could show the possible causes of particle adders during exposure in scanners.

EUV mask defect analysis from mask to wafer printing

ASML NXE3100 has been introduced for EUV Pre-Production, and ASML NXE3300 for High Volume Manufacturing will be installed from this year. EUV mask defect control is the one of the concerns for introducing EUVL to device manufacturing, for current EUV mask defect level is too high to accept for device volume production. EUV mask defects come from mask blank, mask process and mask handling. To have reduced mask defect level, quality control of blank mask, optimization of EUV mask process and improvement of EUV mask handling need to be ready. In this paper, we analyze printed defects exposed from EUV full field mask at NXE3100. For this analysis we trace mask defects from mask to wafer printing. From this we will show current EUV mask’s defect type and numbers. Acceptable defect type, size and numbers for device manufacturing with EUVL will be shown. Through investigating printing result of natural ML defects, realistic level of natural ML defects will be shown.

Practical flare compensation strategy for DRAM device

Flare is hard to control only by hardware-wise means in EUV lithography. Therefore flare compensation through layout correction is necessary. PSF is measured along various slit positions by using clearing resist pad with various sizes in EUV Alpha Demo Tool (ADT) in IMEC. The measured PSF is compared to that derived from mathematically calculated PSD modeling from surface roughness of the projection optics by suppliers. Degree of variation in flare level of real device is measured experimentally with real device layout with clearing pads in it. Flare is calculated as convolution of PSF (Point Spread Function) and pattern density. This requires astronomical amount of computational time, because PSF in EUV has a very long tail that could even reach around several tens of thousands micron range. Therefore we investigated the pattern density of real devices with increasing radius of annulus. If the pattern densities in each annulus are saturated in some level, convolution integral with shorter range is sufficient and longer tail part of PSF can be approximated with fixed DC flare level dependent on saturated pattern density. Finally we discuss about the pending issues regarding flare correction for real devices application of EUV lithography.

EUV-patterning characterization using a 3D mask simulation and field EUV scanner

In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node. EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric characteristics of EUV scanner, shadowing effect produces CD variation versus field position[1][2]. Besides, it is well known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing effect and flare level are one of the important issues for EUV lithography. In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and space pattern is calculated.