Hyun-Chul Park

Design of a High-Efficiency and High-Power Inverted Doherty Amplifier

In this paper, we present a design method for a compact inverted Doherty power amplifier (IDPA), which has high-efficiency and high-power characteristics. An optimum load matching network and an additional offset line, after the matching network of the carrier amplifier, dynamically modulate the load impedance according to the input power drive, while the conventional Doherty power amplifier uses a quarter-wave line to do it. The operational principles and design guide are provided. For experimental verification, a 50-W Doherty amplifier was designed for the pi/4 differential quadrature phase-shift keying application at the 860-MHz band. The measured performance of the IDPA was compared with that of the balanced class-AB amplifier with the same output matching network. At an output power of 50 W, the IDPA performs with 3.16 dB better adjacent channel power ratio (-28 versus -24.84 dBc) and 6.15% higher power-added efficiency (59.02 versus 52.87%) than the class-AB amplifier does.

A New Envelope Predistorter With Envelope Delay Taps for Memory Effect Compensation

We present a new linearization method for high-power amplifiers, using an envelope predistorter (EPD) including envelope delay taps and control circuits, for memory effect compensation. The lower and upper third-order intermodulation (IM3) components, generated by the EPD, can be separately controlled for their magnitudes and phases by the additional memory effect compensation circuits. By using experimental results for a high-power (30-W peak envelope power) class-AB amplifier, further linearity improvement was also demonstrated using the proposed EPD. For a two-tone signal with a tone spacing of 20 MHz, the proposed EPD, with only a single delay tap, cancelled the lower and upper IM3 components by 20.84 and 18.17 dB, while the conventional EPD, with no envelope delay tap, cancelled them by 11.67 and 8.50 dB, respectively

A New Compact Load Network for Doherty Amplifiers Using an Imperfect Quarter-Wave Line

In this paper, we propose a new compact load network for high-power Doherty amplifiers using an imperfect quarter-wave line. A compact pi-network quarter-wave transmission line, which consisted of two shunt capacitors and a series microstrip line, was used to replace a bulky microstrip transmission line. A simple L-C matching network was then deployed after the quarter-wave line. To take the inherent internal parasitic components in the packaged high-power transistors into account, the shunt capacitors of the pi-network quarter-wave transmission line were readjusted, which made an imperfect quarter-wave line. For verification, both the conventional and compact Doherty amplifiers were designed and implemented for the 859-MHz band using high-voltage laterally diffused metal-oxide-semiconductor field-effect transistors. The measured linearities and efficiencies of both amplifiers were compared to each other with respect to the reference performance of the class-AB amplifier for two-tone and down-link wideband code-division multiple-access signal excitations. The compact Doherty amplifier with a significantly reduced size for the load network by 75.7% performed even better than the conventional Doherty amplifier.

High-Efficiency Class-F Amplifier Design In the Presence of Internal Parasitic Components of Transistors

In this paper, the authors present an efficient design method for high efficiency class-F amplifiers considering active devices with internal parasitic components. Considering internal drain current/voltage waveforms observed at the internal drain current source of the transistor, harmonics control and fundamental matching circuits are optimized to have higher power-added efficiency (PAE). Two 1.2GHz amplifiers were designed using a large-signal model of an LDMOSFET: one had harmonics control circuits optimized for external current/voltage waveforms and another had them optimized for internal waveforms. Simulation of the class-F amplifiers with two different output networks was conducted. Class-F amplifiers having an output network optimized for internal waveforms had 19% higher PAE (79% versus 60%)

A 60-W Multicarrier WCDMA Power Amplifier Using an RF Predistorter

In this brief, we present a 60-W power amplifier that is linearized using an RF predistorter for multicarrier wideband code-division multiple-access (WCDMA) applications. The proposed RF predistorter is fully composed of RF or analog circuits, and it has a moderate memory effect compensation capability using a delayed third-order intermodulation (IM3) component path. It also includes the IM5 generation circuits and a compact IM3 generator that is capable of autocanceling for the fundamental component. The proposed RF predistorter was implemented and applied to a 60-W high-power WCDMA amplifier. For a four-carrier downlink WCDMA signal, the RF predistorter improved the adjacent channel leakage power ratio at a 5-MHz offset by 6.19 dB at an average output power of 48 dBm. The total efficiency of the system is as high as 13.6% at the same output power level. At an output power level of 60 W, the linearized power amplifier complies with the linearity specification of the WCDMA system.

Buffer flush and address mapping scheme for flash memory solid-state disk

The flash memory solid-state disk (SSD) is emerging as a killer application for NAND flash memory due to its high performance and low power consumption. To attain high write performance, recent SSDs use an internal SDRAM write buffer and parallel architecture that uses interleaving techniques. In such architecture, coarse-grained address mapping called superblock mapping is inevitably used to exploit the parallel architecture. However, superblock mapping shows poor performance for random write requests. In this paper, we propose a novel victim block selection policy for the write buffer considering the parallel architecture of SSD. We also propose a multi-level address mapping scheme that supports small-sized write requests while utilizing the parallel architecture. Experimental results show that the proposed scheme improves the I/O performance of SSD by up to 64% compared to the existing technique.

The Efficiency Improvement of a Compact Inverted Doherty Amplifier Using Bias Line Adjustment

We describe our proposal of an efficiency improvement method for a compact inverted Doherty amplifier using a bias line adjustment. In order to compensate for the capacitive parasitic components of the high-power transistors, we adjusted a lambda/4 bias line to have an inductive impedance value. The inductive bias line made parallel resonance with the capacitive internal component. The following matching network and offset line rotated the output reflection coefficient (GammaOUT) to almost -1, which was desirable for the compact inverted Doherty amplifier design. The optimum length of the bias line was found after some adjustments. Compared to the Doherty amplifier using a lambda/4 bias line, the proposed Doherty amplifier using an adjusted bias line provided improved power-added efficiencies (PAEs) of 6% and 4% points for a two-tone signal at an output power of 45 dBm and for the pi/4-DQPSK signal at an output power of 47 dBm, respectively.

A 30 W Cartesian Feedback Transmitter with 40 % Efficiency Incorporating an Inverted Doherty Amplifier

We present a 30 W Cartesian feedback transmitter with an efficiency of 40 % and an adjacent channel leakage power ratio (ACLR) of -51 dBc for 859 MHz band pi/4-DQPSK applications. The high efficiency of the system was achieved by a significant efficiency improvement for the final amplifier stage using a load modulation technique. The implemented Cartesian feedback transmitter, using a Doherty power amplifier, exhibited a 3rd order inter-modulation distortion (IMD3) improvement of 27 dB for a two-tone signal at an output power level of 45 dBm. It also had ACLR improvement of 16.2 dB for the pi/4-DQPSK signal at an output power level of 45 dBm. The system performed with an efficiency as high as 40 % which was an improved value by about 7 % points as a consequence of the high efficiency characteristics of the inverted Doherty amplifier.

A RF predistorter using a delay mismatch for an additional IM 3 path

We describe a RF predistorter (RFPD) which has multiple intermodulation (IM) paths for individual cancellation of IM3 and IM5 components. To compensate for the memory effect of the power amplifier and improve the linearization ability of the predistorter, we attached an additional IM3 path to the predistorter which had a delay mismatch against the original IM3 path. The optimized delay mismatch, phase, and magnitude of the additional IM3 components enabled the RFPD to moderately compensate for the memory effect of the IM3 components which were generated by the main amplifier. The proposed RFPD was experimentally verified at the 2.14 GHz band. Using a two-tone signal with a tone spacing of 20 MHz, the lower and upper IM3 components were cancelled by 26.21 and 22.84 dB, respectively. Without an additional IM3 path, the lower and upper IM3 components were only cancelled by 17.11 and 12.68 dB, respectively.

High-Power Cartesian Feedback Transmitter Design for 860 MHz Band

This paper presents the design of 860 MHz band transmitter for improving power amplifier`s linearity using Cartesian feedback method. For eliminating the effects of gain, phase mis-match, and DC offset, we estimate the property variations using ADS software. The implemented Cartesian feedback transmitter exhibits IMD3 of -54 dBc at an output power of 43 dBm and this result shows that the linearity is improved for 22.4 dB, compared with the test of the power amplifier without Cartesian feedback system. Thus, we verify that the proposed Cartesian feedback transmitter can be applied to narrow-band transmitter systems.