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Dive into the research topics where Hanjin Cho is active.

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Featured researches published by Hanjin Cho.


international symposium on circuits and systems | 2001

Numerical word-length optimization for CDMA demodulator

Kyungtae Han; Iksu Eo; Kyungsu Kim; Hanjin Cho

This paper presents search methods to optimize word-length for digital systems. Finding the word-length is tedious work when the variables for optimization are numerous. We have proposed sequential and preplanned searches to find optimum word-length, and compared them in terms of the trials. A comparison for a given optimized point is evaluated. We apply them to word-length optimization for a CDMA demodulator, of which requirement is FER of 0.03. Our results show the sequential and the preplanned search have reduced the trials by the rate of 64% and 89%, respectively compared to a full search to optimize the word-length for the CDMA demodulator design.


custom integrated circuits conference | 2005

An implemented of H.264 video decoder using hardware and software

Seongmo Park; Hanjin Cho; Hee-Bum Jung; Duk-Dong Lee

In this paper, we present a design of video single chip decoder for portable multimedia application. The single- chip called as A-MoVa (advanced mobile video ASIC). This chip has mixed hardware/software architecture to combine performance and flexibility. We designed by using the partition between hardware and software block. We developed the architecture of H.264 decoder based on SoC platform. This chip contains 290,000 gates of logics, 670,000 gates of memories and the chip size was 7.5 mm times 7.5 mm which was fabricated using 0.25 micron 4-layers metal CMOS technology


international symposium on information technology convergence | 2007

A Novel Motion Compensated Frame Interpolation Method for Improving Side Information in Distributed Video Coding

Toan Nguyen Dinh; Gueesang Lee; June-Young Chang; Hanjin Cho

In this paper, we address the side information generation problem in distributed video coding (DVC). To decode the current Wyner-Ziv frame, the DVC decoder usually generates side information by using motion compensated frame interpolation (MCFI) algorithms with neighboring decoded key frames. We survey some MCFI algorithms and side information generation methods based on MCFI. We also discuss our novel idea using edge information of decoded frames to generate more accurate interpolated frame. The experimental results show that it is reasonable to use edge information to improve side information at the decoder.


international conference on consumer electronics | 2001

MPEG-4 video codec for mobile multimedia applications

Juhyun Park; Bontae Koo; Seong-Min Kim; Ikgyun Kim; Hanjin Cho

An MPEG-4 video codec (MoVa) has been developed for implementation of video coding applications according to 3G-324M. On 3G-324M, H.263 is mandatory and MPEG-4 is optional. However, MPEG-4 is proper for mobile multimedia applications (IMT-2000) by its error resilient and concealment tools. It can perform 30 frames/s of QCIF (SQCIF) or 15 frames/s of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. It meets the requirements for MPEG-4 SP@L2. A high bit rate and several sizes of video format are adequate for many applications, like videoconferencing, surveillance, news, or entertainment.


international symposium on circuits and systems | 2000

An area efficient video/audio codec for portable multimedia application

Seongmo Park; Seong-Min Kim; Kyeongjin Byeon; Jinjong Cha; Hanjin Cho

In this paper, we present an area efficient video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as VASP (Video Audio Signal Processor) consists of a video signal processing block and an audio signal processing block. This chip has a mixed hardware/software architecture to combine performance and flexibility. The video signal processing block was designed to implement hardwired solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bit RISC type internal controller. The audio signal processing block is implemented with a software solution using 16 bit fixed point DSP. This chip contains 142,300 gates, 22 kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size was 9.02 mm/spl times/9.06 mm which was fabricated using 0.5 micron 3-layers metal CMOS technology.


international soc design conference | 2008

Star-Mesh NoC based multi-channel H.264 decoder design

June-Young Chang; Wonjong Kim; Younghwan Bae; Mi-Young Lee; Juyeob Kim; Hanjin Cho

In this paper we described the architectural exploration of Star-Mesh NoC based multi-channel H.264 decoder. The Star-Mesh NoC is comprised of local star switch and global mesh switch. By analyzing data transfers among the processors, IPs, and memories, we partitioned IPs into clusters to map then to Star-Mesh NoC architecture. In order to enhance data parallelism and NoC utilization, H.264 decoder IPs with much data traffic are mapped to star switch and shared memory is connected to mesh switch where star switch connected to mesh switch with 1-hop. We explored several mapping architecture to achieve improvement of the system throughput.


international symposium on circuits and systems | 2002

An efficient architecture of DCTQ module in MPEG-4 video codec

Kibum Suh; Seongmo Park; Seong-Min Kim; Bontae Koo; Igkyun Kim; Kyung Soo Kim; Hanjin Cho

In this paper, a VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the DCTQ is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling CIF image formats. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27 MHz clock. The area is 50 % smaller than the previous methods with 2D-DCT and IDCT. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.


international symposium on signal processing and information technology | 2008

Anisotropic Diffusion for Preservation of Line-edges

HyeSuk Kim; Gi-Hong Kim; Gueesang Lee; June-Young Chang; Hanjin Cho

In existing approaches, diffusion is performed in four directions (North, South, East, West) without specific conditions. Therefore, these methods have shortcomings of distorted with the existence of impulse noises. In this paper, a new anisotropic diffusion based on directions of line-edges is proposed to enhance preservation of line-edges together with removal of noises. In the proposed method, an edge detection mask is used to find the direction of a line-edge. As a result, when the magnitude of edge detection is large enough, there exists a line-edge. In the case of a line-edge, the weight of diffusion is selected adaptively according to the direction of the line-edge. The diffusion is based on 8-directions diffusion with emphasis on the line-edge direction. Experimental results show that the proposed method can eliminate noise while preserving contour of line-edges.


Etri Journal | 2005

An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder

Kibum Suh; Seongmo Park; Hanjin Cho


Etri Journal | 2006

VLSI Implementation of H.264 Video Decoder for Mobile Multimedia Application

Seong Mo Park; Mi-Young Lee; Seungchul Kim; Kyoung-Seon Shin; Igkyun Kim; Hanjin Cho; Hee-Bum Jung; Duk-Dong Lee

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Seongmo Park

Electronics and Telecommunications Research Institute

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Mi-Young Lee

Electronics and Telecommunications Research Institute

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June-Young Chang

Electronics and Telecommunications Research Institute

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Seungchul Kim

Electronics and Telecommunications Research Institute

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Wonjong Kim

Electronics and Telecommunications Research Institute

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Duk-Dong Lee

Kyungpook National University

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Hee-Bum Jung

Electronics and Telecommunications Research Institute

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Jinjong Cha

Electronics and Telecommunications Research Institute

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Seong-Min Kim

Electronics and Telecommunications Research Institute

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Younghwan Bae

Electronics and Telecommunications Research Institute

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