Sung-wook Kwon

Design of a High-Efficiency and High-Power Inverted Doherty Amplifier

In this paper, we present a design method for a compact inverted Doherty power amplifier (IDPA), which has high-efficiency and high-power characteristics. An optimum load matching network and an additional offset line, after the matching network of the carrier amplifier, dynamically modulate the load impedance according to the input power drive, while the conventional Doherty power amplifier uses a quarter-wave line to do it. The operational principles and design guide are provided. For experimental verification, a 50-W Doherty amplifier was designed for the pi/4 differential quadrature phase-shift keying application at the 860-MHz band. The measured performance of the IDPA was compared with that of the balanced class-AB amplifier with the same output matching network. At an output power of 50 W, the IDPA performs with 3.16 dB better adjacent channel power ratio (-28 versus -24.84 dBc) and 6.15% higher power-added efficiency (59.02 versus 52.87%) than the class-AB amplifier does.

Inverted-load network for high-power Doherty amplifier

In this article, a high-power, high-efficiency inverted Doherty power amplifier (PA), having a more compact load network than that of the conventional Doherty amplifier, was designed and implemented for wide-band code-division multiple access (WCDMA) base-station applications. Its configuration and working principle are compared with the conventional Doherty amplifier. For experimental verification, we implemented an inverted Doherty amplifier, using a 190 W peak-envelope-power (PEP) laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors (FETs). Using a four-carrier down-link WCDMA signal, we achieved a high power-added efficiency (PAE) of 32% and an average output power level as high as 46.3 dBm at a given adjacent channel leakage ratio (ACLR) level of -30 dBc. This is a 9.5% improvement in efficiency and 1 dB improvement in output power under the same ACLR conditions from those of the balanced class-AB operation using the same devices.

Optimum ASK Modulation Scheme for Passive RFID Tags Under Antenna Mismatch Conditions

We propose optimized ON/OFF states of the backscattered amplitude shift keying (ASK) modulator for the passive RF identification (RFID) tags. This takes into account both the reader receiver sensitivity and tag antenna mismatch conditions. Based on the analysis of the power transfer between the passive RFID tag and reader, we derived the optimum configuration of the ASK modulator. It maximizes the harvestable power to enhance the identification range between the tag and reader. The performance of the proposed modulator configuration was superior to the conventional scheme. We also developed an optimization procedure of the modulator for a given receiver sensitivity of the reader and various antenna mismatch conditions of the tag.

A New Compact Load Network for Doherty Amplifiers Using an Imperfect Quarter-Wave Line

In this paper, we propose a new compact load network for high-power Doherty amplifiers using an imperfect quarter-wave line. A compact pi-network quarter-wave transmission line, which consisted of two shunt capacitors and a series microstrip line, was used to replace a bulky microstrip transmission line. A simple L-C matching network was then deployed after the quarter-wave line. To take the inherent internal parasitic components in the packaged high-power transistors into account, the shunt capacitors of the pi-network quarter-wave transmission line were readjusted, which made an imperfect quarter-wave line. For verification, both the conventional and compact Doherty amplifiers were designed and implemented for the 859-MHz band using high-voltage laterally diffused metal-oxide-semiconductor field-effect transistors. The measured linearities and efficiencies of both amplifiers were compared to each other with respect to the reference performance of the class-AB amplifier for two-tone and down-link wideband code-division multiple-access signal excitations. The compact Doherty amplifier with a significantly reduced size for the load network by 75.7% performed even better than the conventional Doherty amplifier.

Highly sensitive CMOS passive wake-up circuit

We implement a passive wake-up circuit with high voltage sensitivity using standard CMOS technology. We propose voltage multipliers and inverter chain optimized for high voltage sensitivity. The wake-up circuit converts small RF input signals into a DC signal to trigger the interrupt. Using an RF input signal, whose center frequency is 870 MHz and input power is -29.3 dBm, we achieved an output voltage of 0.7 V, enough to trigger on the output. The fully integrated CMOS IC is fabricated using a 0.18 mum standard CMOS process. The chip area is as small as 230 times 190 mum2.

The Efficiency Improvement of a Compact Inverted Doherty Amplifier Using Bias Line Adjustment

We describe our proposal of an efficiency improvement method for a compact inverted Doherty amplifier using a bias line adjustment. In order to compensate for the capacitive parasitic components of the high-power transistors, we adjusted a lambda/4 bias line to have an inductive impedance value. The inductive bias line made parallel resonance with the capacitive internal component. The following matching network and offset line rotated the output reflection coefficient (GammaOUT) to almost -1, which was desirable for the compact inverted Doherty amplifier design. The optimum length of the bias line was found after some adjustments. Compared to the Doherty amplifier using a lambda/4 bias line, the proposed Doherty amplifier using an adjusted bias line provided improved power-added efficiencies (PAEs) of 6% and 4% points for a two-tone signal at an output power of 45 dBm and for the pi/4-DQPSK signal at an output power of 47 dBm, respectively.

A 30 W Cartesian Feedback Transmitter with 40 % Efficiency Incorporating an Inverted Doherty Amplifier

We present a 30 W Cartesian feedback transmitter with an efficiency of 40 % and an adjacent channel leakage power ratio (ACLR) of -51 dBc for 859 MHz band pi/4-DQPSK applications. The high efficiency of the system was achieved by a significant efficiency improvement for the final amplifier stage using a load modulation technique. The implemented Cartesian feedback transmitter, using a Doherty power amplifier, exhibited a 3rd order inter-modulation distortion (IMD3) improvement of 27 dB for a two-tone signal at an output power level of 45 dBm. It also had ACLR improvement of 16.2 dB for the pi/4-DQPSK signal at an output power level of 45 dBm. The system performed with an efficiency as high as 40 % which was an improved value by about 7 % points as a consequence of the high efficiency characteristics of the inverted Doherty amplifier.

A 3.7GHz GaN HEMT Doherty power amplifier using digital predistortion linearization

In this study, we implemented a 3.7 GHz band Doherty amplifier based on GaN HEMTs which was linearized using a digital predistortion method. The forward and reverse models of the predistortion consist of simple polynomials whose coefficients are extracted using a conventional LMSE algorithm. Using two carrier signals based on IEEE 802.16e, whose PAR is 9.44 dB, an ACLR improvement of 10.74 dB was achieved to give an ACLR level of 41.74 dBc at an offset of 4.79 MHz. The overall efficiency of the Doherty power amplifier is 13.74% which represents a 2.44% improvement compared to that of a balanced class-AB power amplifier at an average power of 36 dBm.

Optimum ON/OFF resistances of the ASK modulator for passive RFID tags

In this paper, we propose optimized ON/OFF resistances for the backscattering amplitude-shift keying (ASK) modulator for a passive RFID tag considering the effective backscattered power level. Based on an analysis of power transfer between the passive RFID tag and reader, we obtain the optimal condition for the ASK modulator to maximize the harvestable power. We calculate the performance of the proposed modulator configuration that is superior to the conventional scheme.

A RF predistorter using a delay mismatch for an additional IM 3 path

We describe a RF predistorter (RFPD) which has multiple intermodulation (IM) paths for individual cancellation of IM3 and IM5 components. To compensate for the memory effect of the power amplifier and improve the linearization ability of the predistorter, we attached an additional IM3 path to the predistorter which had a delay mismatch against the original IM3 path. The optimized delay mismatch, phase, and magnitude of the additional IM3 components enabled the RFPD to moderately compensate for the memory effect of the IM3 components which were generated by the main amplifier. The proposed RFPD was experimentally verified at the 2.14 GHz band. Using a two-tone signal with a tone spacing of 20 MHz, the lower and upper IM3 components were cancelled by 26.21 and 22.84 dB, respectively. Without an additional IM3 path, the lower and upper IM3 components were only cancelled by 17.11 and 12.68 dB, respectively.