Hyun-Gi Kim

A 31 ns Random Cycle VCAT-Based 4F

A functional 4F2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the conventional recessed channel access transistor (RCAT). A new design methodology has been applied to accommodate 4F2 cell array, achieving both high performance and manufacturability. Especially, core block restructuring, word line (WL) strapping and hybrid bit line (BL) sense-amplifier (SA) scheme play an important role for enhancing AC performance and cell efficiency. A 50 Mb test chip was fabricated by 80 nm design rule and the measured random cycle time (tRC) and read latency (tRCD) are 31 ns and 8 ns, respectively. The median retention time for 88 Kb sample array is about 30 s at 90°C under dynamic operations. The core array size is reduced by 29% compared with conventional 6F2 DRAM.

^{2}

New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.