Gyo-Young Jin

Scaling and reliability of NAND flash devices

Numerous scaling limitations of NAND flash memory have arisen due to the intrinsic nature of the operational principle of NAND flash memory and those limitations eventually lead to a paradigm shift in the NAND flash technology from the planar cell to the vertical NAND cell. In this paper, the limitations of scaling which induce the evolution of the NAND cell as well as the current trends of NAND technology are reviewed.

A 31 ns Random Cycle VCAT-Based 4F

A functional 4F2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the conventional recessed channel access transistor (RCAT). A new design methodology has been applied to accommodate 4F2 cell array, achieving both high performance and manufacturability. Especially, core block restructuring, word line (WL) strapping and hybrid bit line (BL) sense-amplifier (SA) scheme play an important role for enhancing AC performance and cell efficiency. A 50 Mb test chip was fabricated by 80 nm design rule and the measured random cycle time (tRC) and read latency (tRCD) are 31 ns and 8 ns, respectively. The median retention time for 88 Kb sample array is about 30 s at 90°C under dynamic operations. The core array size is reduced by 29% compared with conventional 6F2 DRAM.

^{2}

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/sup +/ poly gate formed by BF/sub 2/ ion implanted compensation of in situ phosphorus (n/sup +/) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/sup +/- and p/sup +/-doped WSi/sub x/-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/spl kappa/ Al/sub 2/O/sub 3/ and HfO/sub 2/ dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.

DRAM With Manufacturability and Enhanced Cell Efficiency

We studied random telegraph noise (RTN) of n-type and p-type silicon nanowire transistors (SNWT) for the first time and derived accurate vertical and lateral trap location equations in nanowire structure. Using the derived equations, accurate trap locations were extracted in the devices with single trap as well as multiple traps.

A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n/sup +/-doped polysilicon

A novel process technology for 6F/sup 2/ DRAM cell at 68nm design rule was for the first time developed. The cell size is 0.028/spl mu/m/sup 2/, which is the smallest cell size ever reported. ArF lithography with double expose technology and highly selective etching process were used for patterning of critical layers. This 6F cell was made of simple line/space patterns for easy patterning and self-aligned etches to improve process margins. MIM cell capacitor was developed with multi-layer high-k dielectric materials and 11A equivalent Tox and sub-lfA leakage was confirmed.

Random Telegraph Noise in n-type and p-type silicon nanowire transistors

New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.

A 6F/sup 2/ DRAM technology in 60nm era for gigabit densities

Hot carrier (HC) reliability of Gate-All-Around Twin Si Nanowire Field Effect Transistor (GAA TSNWFET) is reported and discussed with respect to size and shape of nanowire channel, gate length, thickness and kind of gate dielectric in detail. Smaller nanowire channel size, shorter gate length and thinner gate oxide down to 2nm thickness show worse hot carrier reliability. The worst VD for 10 years guaranty, 1.31V, satisfies requirement of ITRS roadmap.

Novel 4F 2 DRAM cell with Vertical Pillar Transistor(VPT)

An isotropic two band model is proposed for electrons in silicon, that has the same density of states and magnitude of group velocity as those of the full band structure based on empirical pseudopotential method calculations. The band model and transport parameters are calibrated through extensive comparisons with Monte Carlo simulation results and various experiments related to electron transport in silicon. Specifically, the drift velocity, impact ionization coefficient, quantum yield, 2p core level line intensity and broadening from x‐ray photoemission spectroscopy have all been used in calibration. Through the study of electron emission at the Si/SiO2 interface in metal‐oxide‐semiconductor structures using the Monte Carlo method, it is demonstrated that the model has good accuracy in modeling high field transport phenomena in silicon.

Investigation on hot carrier reliability of Gate-All-Around Twin Si Nanowire Field Effect Transistor

A new program disturbance phenomenon appeared from sub 40nm-node NAND flash cell is presented firstly which is named as BTBT Leakage Burst by Channel Coupling (abbr. “Channel Coupling”). With scaling down, the neighboring program channel of 0V grabs strongly the boosted channel at program-inhibited active line not to rise up at the active sidewall and simultaneously, its potential at Si surface is tried to be raised by help of pass voltage. The competition induces the sharp band-bending and thereby sudden enhancement of BTBT leakage, resulting in suppressing channel boosting. In order to overcome “Channel Coupling” appeared at 1X-nm node as a scaling barrier, the air gap in shallow trench isolation is suggested and the effect of the air gap is verified by simulation.

An isotropic two band model for hot electron transport in silicon: Including electron emission probability into SiO2

Demand for higher bandwidth DRAM continues to increase, especially in high-performance computing and graphics applications. However, conventional DRAM devices such as DDR4 DIMM and GDDR5 cannot satisfy these needs since they are bandwidth limited to less than 30GB/s. Also, if multiple GDDR DRAMs are used simultaneously for higher bandwidth, then high power consumption and routing congestion on PCBs become a big concern. In order to overcome these limitations, the high-bandwidth memory (HBM) DRAM was recently introduced[1]. HBM-DRAM uses TSV and interposer technologies enabling multiple chip stacks and wide I/Os between the processor and memory: providing high capacity, low power and high bandwidth. This paper proposes the 2nd generation HBM to double the bandwidth from 128GB/s to more than 256GB/s and support pseudo-channel mode and 8H stacks [2]. In the pseudo-channel mode, a legacy channel is divided into two pseudo channels and the two pseudo channels share the command-address pins. Thus, one HBM has 16 pseudo channels instead of 8 legacy channels. To support various stack configurations including 8H stacks, a new architecture is adopted for flexible density ranging from 16Gb to 64Gb maintaining the same bandwidth. Finally, the bandwidth increase requires an active thermal solution to manage hotspots that develop from highly concentrated power consumption; we propose an adaptive refresh considering temperature distribution (ART) scheme as a solution.