Jae-Man Yoon

Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60nm technology and beyond

In this paper, a highly manufacturable 512M FinFET DRAM with novel body tied FinFET cell array transistor on bulk Si substrate has been successfully integrated and the characteristics were compared with RCAT (Recess Channel Array Transistor) and planar cell array transistor DRAM for the first time. We also propose the NWL (Negative Word Line) scheme with low channel doping body tied FinFET for a highly manufacturable FinFET DRAM for sub 60nm technology node.

Enhanced data retention of damascene-finFET DRAM with local channel implantation and fin surface orientation engineering

80nm damascene-finFET (d-finFET) 512M DRAM is fabricated on bulk <100> channel directional wafer (CW). We adopted damascene technology to form the fin only to the channel region of cell array transistor with self-aligned LCI (local channel ion implantation). From the reduced contact resistance, surface treatment, and electron mobility improvement of <100> CW, 50% increased on-current is achieved in d-finFET. Utilizing LCI to d-finFET, junction leakage of the storage node has been reduced. The characteristics of d-finFET and conventional finFET (c-finFET), and <110> CW and <100> CW were compared. Using the d-finFET scheme with LCI, data retention time is further improved from the previous work of c-finFET (Lee et al., 2004).

A 31 ns Random Cycle VCAT-Based 4F

A functional 4F2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the conventional recessed channel access transistor (RCAT). A new design methodology has been applied to accommodate 4F2 cell array, achieving both high performance and manufacturability. Especially, core block restructuring, word line (WL) strapping and hybrid bit line (BL) sense-amplifier (SA) scheme play an important role for enhancing AC performance and cell efficiency. A 50 Mb test chip was fabricated by 80 nm design rule and the measured random cycle time (tRC) and read latency (tRCD) are 31 ns and 8 ns, respectively. The median retention time for 88 Kb sample array is about 30 s at 90°C under dynamic operations. The core array size is reduced by 29% compared with conventional 6F2 DRAM.

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Scalability of interface driven perpendicular magnetic anisotropy (i-PMA) magnetic tunnel junctions (MTJs) has been improved down to 1X node which verifies STT-MRAM for future standalone memory. With developing a novel damage-less MTJ patterning process, robust magnetic and electrical performances of i-PMA MTJ cell down to 15 nm node could be achieved.

DRAM With Manufacturability and Enhanced Cell Efficiency

In this paper, we fabricated a BT-FinFET SRAM device with the smallest cell size of 0.46 /spl mu/m/sup 2/. And a hot carrier generation mechanism in the FinFET is thoroughly evaluated by measuring the I/sub sub/ of the BT-FinFET for various Si fin widths (20/spl sim/70 nm). For the first time, we revealed the mechanism of improved hot carrier immunity of sub 50 nm fin type MOSFETs.

Verification on the extreme scalability of STT-MRAM without loss of thermal stability below 15 nm MTJ cell

for 4F2 DRAM Cell Array with sub 40 nm Technology Jae-Man Yoon, Kangyoon Lee, Seung-Bae Park, Seong-Goo Kim, Hyoung-Won Seo, Young-Woong Son, Bong-Soo Kim, Hyun-Woo Chung, Choong-Ho Lee*, Won-Sok Lee* *, Dong-Chan Kim* * *, Donggun Park*, Wonshik Lee and Byung-Il Ryu ATD Team, Device Research Team*, CAEP*, PD Team***, Semiconductor R&D Division, Samsung Electronics Co., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do, 449-711, Korea Tel) 82-31-209-4741, Fax) 82-31-209-3274, E-mail)

Hot carrier generation and reliability of BT(body-tied)-Fin type SRAM cell transistors (W/sub fin/=20/spl sim/70 nm)

In this paper, a highly manufacturable 256 M body tied tri-gate fin array NOR-type Flash memory, with 70 nm fin width, was successfully fabricated and the characteristics were compared with planar cell array transistors. In this experiment, a 1.6 times higher driving current of the fin array flash memory cell transistor is achieved than that of a planar device with the same gate length. We propose an optimized fin structure for flash memory operation and a direction for enhanced current of the fin array flash memory cell transistor with respect to the channel silicon plane, coupling ratio, junction profile and anti-punch through implantation conditions.

A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology

In this paper, a device design guideline of sub 60nm BT-FinFET (Body Tied Fin FET) DRAM cell transistor is proposed. The VT controllability and variation were compared for 3 different implant concepts (blanket, local channel, and asymmetric S/D) and 2 different fin active designs (uneven and straight active type). Those were systemically analyzed for sub 60nm BT-FinFET device. And finally, the optimal structure for mass production is discussed. Introduction Body tied FinFET cell DRAM has been intensively investigated [1-2] to introduce this technology to mass production early as possible. And NWL (Negative Word Line) and damascene technology were successfully applied to 512M FinFET DRAM. Based on the damascene FinFET DRAM process, LCI (Local Channel Implantation) on FinFET was shown excellent data retention time owing to reducing unnecessary boron dopant at the n+ storage node and nregion. And <100> channel direction scheme was also introduced to increase the saturation current and speed by maximize the electron mobility. However, the boron dopant at the LCI region diffuses to the storage node resulting in unwanted junction leakage increment. And the saucer type uneven active was not effective for using <100> CW (Channel direction Wafer) [4] because it has a concaved channel direction. Therefore, we have investigated a design of active fin and channel VT control methods. In this paper, we present several critical points of device design consideration of body tied FinFET DRAM such as the active fin design, NWL, refresh characteristics and FinFET VT control. Experimental The highly manufacturable 512M damascene BT-FinFET DRAM was integrated on p-type bulk Si (100) wafer by using 80nm body tied finFET process technology [2] (Fig. 1-(a)). And LCI (Local Channel Implantation), Blanket and ASD (Asymmetric Source Drain) implantation methods (Fig. 1-(b)) were split on d-FinFET (damascene FinFET) DRAM having 2 different active designs (Fig. 2). As can be seen clearly, straight active designed FinFET shows uniform fin width of 60nm from storage node edge “A” to bit line node edge “B” while uneven active FinFET shows thicker fin width at “B” side. The refresh characteristics of FinFET DRAM were evaluated for negative word line potential versus FinFET threshold voltage and 3 different implantation schemes. Results and Discussion The dynamic and static refresh characteristics of 512M d-FinFET were evaluated to find a relationship between NWL and VTC (Threshold voltage of Cell Tr.) of FinFET (Fig. 3). It is shown that approximately -0.6 ~ -0.8V range of NWL potential was required to minimize both dynamic and static fail bit for a FinFET cell Tr. having low (~0.1V) cell threshold voltage. And the range can be increased when higher VTC was used because the dynamic refresh fail was suppressed at lower NWL where the increasing of static fail bit is still negligible. Therefore, the minimum VTC was found to accomplish the operational refresh margin. However, the threshold voltage adjustment is more difficult for thinner body FinFET due to segregation of boron at the 3D fin surface. And it is ultimately difficult for DRAM because storage node junction leakage current is very sensitive to increasing of boron dopant. ASD (Asymmetric Source Drain) implantation scheme was then applied to minimize the boron effects on storage node junction leakage. Fig. 4 shows ASD device having the lowest storage node junction leakage current over the blanket implant and LCI scheme. However, the bit line node leakage current difference was minimized which has negligible effect on refresh characteristics. In Fig. 6, the threshold voltage controllability of uneven and straight type active design. ASD implantation was used and found that the VT control of uneven active FinFET can be easier than that of straight active. It was important result because the uneven active has been conventionally used to achieve enough alignment margins after gate pattering for bit line contact. Fig. 7 shows Id-Vg characteristics of ASD implanted FinFET DRAM cell. It indicates one cell transistor can have two different VT for operation conditions and VT of write “1” condition is about 350mV lower than read “1” condition. It is a great advantage that the data “1” can be easily written for ASD FinFET. However, the threshold voltage distributions of both active designs indicate a demerit of uneven active FinFET cell transistor (Fig. 8). Also VT distribution of 80nm RCAT (Recess Channel Array Transistor) [3], FinFET with ASD and thin body transistor with TiN gate were compared. The uneven active FinFET with ASD shows large VT distribution while recess channel array transistor and straight active FinFET with ASD show negligible distribution. It is quit clear that RCAT or straight active design is acceptable for mass production. However, FinFET cell array transistor has several advantages over RCAT besides VT distribution for being used sub 60nm regime [1]. Therefore, based on these result, the optimal design scheme of FinFET DRAM is straight active combined with ASD or workfunction optimized gate since NWL (Negative Word Line) scheme was found to be an optimal solution for body tied FinFET DRAM. Finally, the refresh characteristics of 3 different VT adjustment implant scheme were evaluated (Fig. 10) and found the ASD implanted 512M FinFET DRAM shows superior characteristics over the others. Fig. 11 shows the expected VT of sub 40nm FinFET cell DRAM by using 4.7 ~ 5.1eV gate material and minimum required VT can be lowered for FinFET with NWL and high workfunction gate material while maintaining minimum Ion/Ioff ratio requirement of 10. Conclusion In this paper, we systemically analyze 80nm body tied FinFET cell array transistor DRAM for the fin active design and device design schemes. Based on consideration of VT controllability, distribution and refresh margin, straight active design with ASD (Asymmetric Source Drain) scheme was found to be the best structure for production of BT-FinFET DRAM. References [1] C. H. Lee, et al., VLSI 2004, 13.3, p130. [2] C. Lee, et al., IEDM 2004, 3.2, p61. [3] H. S. Kim, et al., IEDM 2003, 17.2, p411. [4] T. Komoda, et al., IEDM2004, 9.3, p217. Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials, Kobe, 2005, -184H-1-2 pp.184-185