Hyun Kyu Yu

A novel approach to extracting small-signal model parameters of silicon MOSFET's

We present a simple and accurate method to extract a small-signal equivalent circuit model of Si MOSFETs, based on the novel approach to determining parasitic inductances and resistances by fitting the frequency response of new analytic expressions with Z-parameters. This method is proposed to overcome the serious problem that conventional cold-FET methods cannot be applied for MOSFETs, and is also superior to the traditional optimization of the entire model parameters to fit the measured S-parameters. In particular, this technique is simple and reliable because no additional measurements are needed. The excellent correspondence is achieved between modeled and measured S-parameters from 0.5 to 39.5 GHz.

Variable inductance multilayer inductor with MOSFET switch control

A variable monolithic inductor having a stacked spiral inductor connected with MOSFET switches is proposed and fabricated in a 0.18 /spl mu/m, one-poly-six-metal (1P6M) standard CMOS process. By controlling a voltage of the MOSFET switch, the proposed three-stacked inductor demonstrates a continuously variable inductance of from 8 to 23 nH at 2.4 GHz, and due to its stacked structure, it takes less than 50% of the chip area compared with conventional single layer inductors. With its compact size and variable inductance feature, the proposed variable inductor is a prospective key component for the multiband RF circuits such as electrically controllable matching circuits and wide tuning range voltage controlled oscillators (VCOs).

The detailed analysis of high Q CMOS-compatible microwave spiral inductors in silicon technology

We present the extensive experimental results and their detailed analysis showing the important effects of layout parameters on the frequency responses of quality factor (Q) of rectangular spiral inductors, which are fabricated on a silicon substrate by using conventional silicon CMOS technology, in order to determine the desirable values of layout parameters for designing the high Q inductors used in RF ICs applications. Analysis of the inductors on Si substrates with three kinds of resistivities has been performed by tailoring the geometric layout and varying the metal thickness. Using these results, the substrate effects on RF performance of inductors are also investigated by observing the frequency responses of Q with varying the substrate resistivity in detail.

A small-signal RF model and its parameter extraction for substrate effects in RF MOSFETs

We propose a physically acceptable small-signal model incorporating substrate effects, in order to eliminate the severe frequency-dependence of the intrinsic drain-source resistance observed from a conventional model of RF Si MOSFETs. This model is based on the substrate network where a parallel RC circuit is connected in series with the drain junction capacitance. It is demonstrated that the substrate effects result in the frequency-dispersion of the effective drain-source resistance and capacitance below 10 GHz. An accurate extraction technique using a simple curve-fit approach is developed to determine substrate parameters directly, and their bulk voltage-dependencies are presented in detail. The validity of this model is partially proved by finding intrinsic parameters exhibiting frequency-independence up to 10 GHz. Better agreement with measured S-parameters is achieved by using the new substrate model rather than the conventional one, verifying the accuracy of the physical model and extraction technique.

Gate layout and bonding pad structure of a RF n-MOSFET for low noise performance

Several 0.35 /spl mu/m n-MOSFETs with different gate geometry were analyzed to maximize the RF performance, after that the pads were shielded to ground to reduce the noise contribution of pads. The F/sub min/ of 0.5 dB was improved by utilizing the ground-shielded pads, and the F/sub min/ of 0.2 dB was improved by using the double-sided gate contact type. The n-MOSFET having the single-sided gate contact and ground-shielded pad showed the F/sub min/ of 0.46 dB and 0.37 dB at 2 GHz with the drain current of 2.0 mA and 5.3 mA, respectively. Furthermore, the weak frequency dependency of the F/sub min/ showed a great possibility of a low noise amplifier above 5 GHz.

Frequency-dependent series resistance of monolithic spiral inductors

We present the analysis of the frequency dependent inductor series resistance (R/sub s/). The high-frequency effects on series resistance have been confirmed with measured and simulated data of inductors having different geometric and process parameters in order to predict and optimize the high-performance inductors used in radio frequency (RF) integrated circuits (ICs). The results show that the magnetic field effect seems to be a dominant factor in determining the R/sub s/ in the high-frequency region.

CMOS layout and bias optimization for RF IC design applications

High frequency and low noise performance of 0.8 /spl mu/m polysilicon gate CMOS device has been analyzed intensively with the various multi-finger polysilicon gate layout and bias to find the optimal condition. From the analysis, the optimal width of unit gate finger and bias condition have been found to maximize f/sub max/ and minimize F/sub min/. At the conditions, F/sub min/, gain and noise resistance characteristics of large width transistors are also analyzed.

High Q microwave inductors in CMOS double-metal technology and its substrate bias effects for 2 GHz RF ICs application

This paper presents high quality factor (Q) microwave inductors (up to 20) fabricated on a high-resistivity substrate with a thick-metal layer integrated by using only CMOS double-metal interconnection technology for 2 GHz RF ICs applications. A quality factor Q of 20.1 at 3.25 GHz for 11.9 nH-inductor has been achieved. Also we report a low-loss substrate bias technique to improve the Q of the inductors.

Linearity, noise optimization for two stage RF CMOS LNA

Deep sub-micron CMOS technology is a good candidate for a wireless communication RF IC because of the integration possibility of IF and RF modules together. For optimum noise performance, the CMOS transistor layout and bias condition are analyzed and discussed. In this paper along with the noise optimum condition, a linearity improvement technique for a cascaded LNA is presented. The LNA for mobile applications should satisfy the noise, linearity and gain performance under the current consumption constraint. If an LNA is designed with more than a two stage structure, then the first stage MOS ought to be optimized for low noise performance in terms of the bias condition and its size because the first stage MOS is the dominant noise contributor of all the cascade stage. The last stage is constructed for linearity optimization, because the last stage linearity is influential for a cascaded LNA.

A semianalytical parameter extraction of a SPICE BSIM3v3 for RF MOSFET's using S-parameters

In this paper, we present a new parameter-extraction method combining analytical and optimization approaches for the RF large-signal Berkeley Short-Channel IGFET Model 3, Version 3.0. Using S-parameters of MOSFETs with different channel lengths and widths at zero gate bias, all overlap capacitances are accurately determined in the high-frequency range. The junction-capacitance model parameters are extracted using S-parameters of devices with different perimeter-to-area ratios at two different biases of zero and high voltages. A robust technique utilizing simple Z-parameter equations is also used to extract resistances (R/sub g/ and R/sub d/) and inductances. The source and substrate resistances are initially determined using the zero-bias optimization, and their uncertainties are subsequently eliminated in the normal-bias optimization. Good agreements between measured and modeled S-parameters from 0.5 to 12 GHz demonstrate the validity of this semianalytical method.