Jin-Gun Koo

High-voltage power integrated circuit technology using SOI for driving plasma display panels

A new high-voltage (HV) power IC technology using high-performance p-LDMOS transistors and an excellent dielectric isolation technology has been proposed to apply the scan driver of color plasma display panel (C-PDP) system. This novel technique reduces over 40 process steps and results in smaller chip size area of the developed scan driver than that of conventional driver using conventional power IC technology. The chip size and the rise time of the PDP scan driver IC developed by this technology could be reduced by 35% and 60%, respectively, compared with the conventional design.

Novel process techniques for fabricating high density trench MOSFETs with self-aligned N/sup +//P/sup +/ source formed on the trench side wall

Novel process techniques for fabricating highly dense trench MOSFETs are proposed and verified by experimental and numerical results. P/sup +/ region for p-base contact and N/sup +/ source are formed on the trench side wall by using self-aligned process techniques including triple trench etching. Two-dimensional process and device simulation is performed by using SILVACO with the cell pitch of 1.0 /spl mu/m for the proposed trench MOSFET. The simulated breakdown voltage and on-resistance are 45 V and 12.9 m/spl Omega/-mm/sup 2/, respectively.

Improvement of P-channel SOI LDMOS transistor by adapting a new tapered oxide technique

On-resistance of P-channel REduced SURface Field (RESURF) lateral double-diffused MOS (LDMOS) transistors has been improved by using a new tapered TEOS field oxide on the drift region of the devices. The new tapered oxidation technique provides better uniformity, less than 3%, and reproducibility. With the similar breakdown voltage (V/sub B/), at V/sub gs/=-5.0 V, the specific on-resistance (R/sub sp/) of the LDMOS with the tapered field oxide is about 31.5 m/spl Omega//spl middot/cm/sup 2/, while that of the LDMOS with the conventional field oxide is about R/sub sp/=57 m/spl Omega//spl middot/cm/sup 2/. The uniformities of R/sub sp/ and V/sub B/ are less than 5 and 3%, respectively.

A novel trench formation and planarization technique using positive etching and CMP for smart power ICs

A new trench isolation technique has been demonstrated which can be used to make high voltage integrated circuits with trench isolation. The technique consists of positive etching using HBr and SiF/sub 4/ chemistries with 45% He-O/sub 2/ additives and global planarization after trench refill techniques using chemical-mechanical polishing (CMP). The novel technique provides better surface quality of 3.1 /spl Aring/ RMS roughness as measured by AFM, better CMP uniformity of less than 3%, and better leakage characteristics of less than 1 nA at 400 V.

Effects of the Resistivity and Crystal Orientation of the Silicon PIN Detector on the Dark Current and Radiation Response Characteristics

The effects of the resistivity and crystal orientation on the leakage current and radiation response characteristics have been studied. The detector with (111) oriented substrate shows higher leakage current than (100) orientation due to the higher interface trap density at the Si/SiO2 interface. And high resistive substrate shows larger leakage current than low resistive one because of its wider depletion width at the same bias voltage. However, in case of (100) oriented substrate, the leakage current of low resistive substrate is larger than high resistive substrate at high reverse bias. It seems that thermionic field emission (TFE) current for low resistive substrate increased at high reverse bias. To compare the charge generation and collection for the radiation, we irradiated an X-ray beam to each detector and read the output current. The detector with (111) oriented substrate shows 20% higher output current than (100) orientation and it is independent on the resistivity of the substrates. The most influential factor on the output current is the thickness of the wafer. From the results we can suggest a high resistive, (100) oriented and thick wafer for direct type radiation detector, and a low resistive and thin wafer for in-direct type detector. Finally, we assembled our detector with read-out integrated circuit for the application of gamma ray dosimeter and our detector is very sensitive to Cs137 natural gamma ray.

Ni-63 radioisotope betavoltaic cells based on vertical electrodes and pn junctions

3D Silicon pn junction betavoltaic cells are designed and fabricated with vertical electrode structure in this work. The betavoltaic cells consist of multiple vertical pn junctions generated by the vertical p-electrodes. The beta-particles from beta-emitting radioisotope Ni-63 are directly incident to the space charge region of vertically generated pn junctions without passing the neutral n or p region. The energy conversion from nuclear energy to electric energy occurs at the vertically generated space charge region. The electrical characteristics of betavoltaic cells having three different unit pn electrode spacing, i.e. 50, 110, and 190μm are demonstrated using electron beam irradiation in a scanning electron microscope (SEM). The Voc and Jsc as a function of pn spacing under 17keV and 30keV of acceleration voltage onto 1.2 × 1.2 mm2 of unit cell absorption area are presented in this paper.

The fabrication of bolometric IR detector for glucose concentration detection

A vanadium pentoxide ()-based bolometric infrared (IR) sensor has been designed and fabricated using micro electro mechanical systems (MEMS) technology for glucose detection and its resistive characteristics has been illustrated. The proposed bolometric infrared sensor is composed of the vanadium pentoxide array that shows superior temperature coefficient of resistance (TCR) and standard silicon micromachining compatibility. In order to achieve the best performance, deposited thin film is optimized by adequate rapid thermal annealing (RTA) process. Annealed vanadium oxide thin film has demonstrated a linear characteristic and relatively high TCR value (). The resistance of vanadium oxide is changed by IR intensity based on glucose concentration.

Fabrication of a direct-type silicon pixel detector for a large area hybrid x-ray imaging device

We demonstrated the design and the fabrication processes of a direct-type silicon pixel detector for a digital dental radiography made using a high-resistive n-type silicon substrate. The structure of the detector is based on a fully-depleted p-i-n diode. The detector is composed of 644,328 pixels with a pitch of 35 mum. The size of the detector is 2.58 cm x 3.47 cm and it is composed of a 4-block assembly with four read-out CMOS ICs. We focused on experimentally evaluating the process conditions for the silicon pixel detector to reduce the leakage current and improve the breakdown voltage. From the experimental results, we found that the high temperature drive-in after p+ ion implantation deteriorates the leakage current and p+ passivation by thermal oxidation improves the breakdown voltage. The leakage current of a pixel was 0.07 pA/pixel and the breakdown voltage was more than 1700 V. The read-out IC consists of a current-integrating pixel readout CMOS chip and PbSn bumps. After bump-bonding four read-out ICs to a pixel detector and wire-bonding to a PCB, X-ray image tests showed a resolution of 11 lp/mm and provided a good image of human teeth.