Hyun-Yong Yu

Germanium In Situ Doped Epitaxial Growth on Si for High-Performance

We demonstrate an abrupt and box-shaped n+/p junction in Ge with a high level of activation of n-type-dopant phosphorus (P) using in situ doping during epitaxial growth. The temperature dependence of dopant activation was investigated associated with the shallower and abrupt junction formation. In addition, we have fabricated high-performance Ge n+/p-junction diodes at 400degC-600degC, based on the in situ doping technique. Excellent diode characteristics having a 1.1 times 104 on/off ratio and a high forward current density (120 A/cm2 at 1 V) are obtained in an n+/p diode at 600-C in situ doping.

\hbox{n}^{+}/\hbox{p}

We demonstrate high performance, 3D IC compatible, Ge n and p-MOSFETs fabricated at very low temperatures, below 380degC. The low temperature gate stack comprises of high-K/metal materials. Very low series resistance (2.23times10-4 Omega-cm at the lowest point of SRP) and shallow (92 nm) source/drain (S/D) junctions with high degree of dopant activation is achieved especially in n-MOSFETs using CMOS process compatible technique - metal (Co) induced dopant activation (Co MIDA) and Ge crystallization. Low S/D resistance in Ge n-MOSFETs has previously been highly challenging. The Ge n-MOSFET, fabricated at 360degC, has an electron mobility comparable to the highest one reported previously, while the Ge p-MOSFET shows a hole mobility higher than the universal Si mobility. The Ge n- and p-MOSFETs provide an excellent Ion/Ioff ratio ( ~1.1times103 for both). In addition to other uses, this low temperature Ge CMOS process serves as a compelling enabler for integrating high performance Ge transistors above metal layers as required by 3D-ICs without exceeding 400degC.

-Junction Diode

We demonstrate normal incidence p-i-n photodiodes on selective-area-grown Ge using multiple hydrogen annealing for heteroepitaxy for the purpose of monolithic integration. An enhanced efficiency in the near-infrared regime and the absorption edge shifting to longer wavelength is achieved due to 0.14% residual tensile strain in the selective-area-grown Ge. The responsivities at 1.48, 1.525, and 1.55 mum are 0.8, 0.7, and 0.64 A/W, respectively, without an optimal antireflection coating. These results are promising toward monolithically integrated on-chip optical links and in telecommunications.

Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and high-k/metal gate stack for monolithic 3D integration

Germanium-on-insulator (GOI) is desired for high performance metal-oxide-semiconductor transistors and monolithically integrated optoelectronics. We demonstrate a promising approach to achieve single-crystal defect-free GOI by using lateral over-growth through SiO2 window. The dislocations due to the lattice mismatch are effectively terminated and reduced in SiO2 trench by selective area heteroepitaxy combined with hydrogen annealing. Low defect density of 4×106 cm−2 and low surface roughness of 0.7 nm (root-mean-square) on GOI are confirmed by plan-view transmission electron microscopy and atomic force microscopy analysis. In addition, the excellent metal-semiconductor-metal diode electrical characteristics fabricated on this GOI confirm Ge crystal quality. The selectively grown GOI structure can provide the monolithic integration of SiGe based devices on a Si very large scale integration (VLSI) platform.

High-Efficiency p-i-n Photodetectors on Selective-Area-Grown Ge for Monolithic Integration

Characterizations of direct gap emission from epi-Ge through both optical and electrical pumping were studied for the application of Si compatible light sources such as on-chip optical interconnect. In-situ doping technique with PH3 during the epi-Ge growth was first applied to achieve high n-type doping concentrations. Photoluminescence (PL) measurements show that the direct band emission of Ge increases with higher doping concentration. This confirms that the Ge direct radiative recombination efficiency can be improved by band filling of electrons. A Ge n+/p light emitting diode (LED) on a Si substrate was then fabricated to study the electroluminescence (EL) properties related to the band filling. Direct band gap EL at 1.6 mu m was also obtained from this Ge LED. Unlike ordinary electrically pumped devices, this LED shows a superlinear luminescence enhancement at high current. Thermal enhancement effects observed in temperature dependent EL spectra show the capability of this device to be operated at room temperature or above.

High quality single-crystal germanium-on-insulator on bulk Si substrates based on multistep lateral over-growth with hydrogen annealing

In the post-Moore era, it is well-known that contact resistance has been a critical issue in determining the performance of complementary metal-oxide-semiconductor (CMOS) reaching physical limits. Conventional Ohmic contact techniques, however, have hindered rather than helped the development of CMOS technology reaching its limits of scaling. Here, a novel conductive filament metal-interlayer-semiconductor (CF-MIS) contact-which achieves ultralow contact resistance by generating CFs and lowering Schottky barrier height (SBH)-is investigated for potential applications in various nanodevices in lieu of conventional Ohmic contacts. This universal and innovative technique, CF-MIS contact, forming the CFs to provide a quantity of electron paths as well as tuning SBH of semiconductor is first introduced. The proposed CF-MIS contact achieves ultralow specific contact resistivity, exhibiting up to ∼×700 000 reduction compared to that of the conventional metal-semiconductor contact. This study proves the viability of CF-MIS contacts for future Ohmic contact schemes and that they can easily be extended to mainstream electronic nanodevices that suffer from significant contact resistance problems.