Duygu Kuzum

Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing

Brain-inspired computing is an emerging field, which aims to extend the capabilities of information technology beyond digital logic. A compact nanoscale device, emulating biological synapses, is needed as the building block for brain-like computational systems. Here, we report a new nanoscale electronic synapse based on technologically mature phase change materials employed in optical data storage and nonvolatile memory applications. We utilize continuous resistance transitions in phase change materials to mimic the analog nature of biological synapses, enabling the implementation of a synaptic learning rule. We demonstrate different forms of spike-timing-dependent plasticity using the same nanoscale synapse with picojoule level energy consumption.

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

Synaptic electronics: materials, devices and applications

In this paper, the recent progress of synaptic electronics is reviewed. The basics of biological synaptic plasticity and learning are described. The material properties and electrical switching characteristics of a variety of synaptic devices are discussed, with a focus on the use of synaptic devices for neuromorphic or brain-inspired computing. Performance metrics desirable for large-scale implementations of synaptic devices are illustrated. A review of recent work on targeted computing applications with synaptic devices is presented.

An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation

The multilevel capability of metal oxide resistive switching memory was explored for the potential use as a single-element electronic synapse device. TiN/HfOx/AlOx/ Pt resistive switching cells were fabricated. Multilevel resistance states were obtained by varying the programming voltage amplitudes during the pulse cycling. The cell conductance could be continuously increased or decreased from cycle to cycle, and about 105 endurance cycles were obtained. Nominal energy consumption per operation is in the subpicojoule range with a maximum measured value of 6 pJ. This low energy consumption is attractive for the large-scale hardware implementation of neuromorphic computing and brain simulation. The property of gradual resistance change by pulse amplitudes was exploited to demonstrate the spike-timing-dependent plasticity learning rule, suggesting that metal oxide memory can potentially be used as an electronic synapse device for the emerging neuromorphic computation system.

Transparent and flexible low noise graphene electrodes for simultaneous electrophysiology and neuroimaging

Calcium imaging is a versatile experimental approach capable of resolving single neurons with single-cell spatial resolution in the brain. Electrophysiological recordings provide high temporal, but limited spatial resolution, because of the geometrical inaccessibility of the brain. An approach that integrates the advantages of both techniques could provide new insights into functions of neural circuits. Here, we report a transparent, flexible neural electrode technology based on graphene, which enables simultaneous optical imaging and electrophysiological recording. We demonstrate that hippocampal slices can be imaged through transparent graphene electrodes by both confocal and two-photon microscopy without causing any light-induced artefacts in the electrical recordings. Graphene electrodes record high-frequency bursting activity and slow synaptic potentials that are hard to resolve by multicellular calcium imaging. This transparent electrode technology may pave the way for high spatio-temporal resolution electro-optic mapping of the dynamic neuronal activity.

Ge-Interface Engineering With Ozone Oxidation for Low Interface-State Density

Passivation of Ge has been a critical issue for Ge MOS applications in future technology nodes. In this letter, we introduce ozone oxidation to engineer Ge/insulator interface. Density of interface states (D_it) across the bandgap and close to the conduction band edge was extracted using conductance technique at low temperatures. D_it dependence on growth conditions was studied. Minimum D_it of 3 times 10¹¹ cm^-2V^-1 was demonstrated. Physical quality of the interface was investigated through Ge 3d spectra measurements. We found that the interface and D_it are strongly affected by the distribution of oxidation states and the quality of the suboxide.

Bioresorbable silicon electronics for transient spatiotemporal mapping of electrical activity from the cerebral cortex

Bioresorbable silicon electronics technology offers unprecedented opportunities to deploy advanced implantable monitoring systems that eliminate risks, cost and discomfort associated with surgical extraction. Applications include post-operative monitoring and transient physiologic recording after percutaneous or minimally invasive placement of vascular, cardiac, orthopedic, neural or other devices. We present an embodiment of these materials in both passive and actively addressed arrays of bioresorbable silicon electrodes with multiplexing capabilities, that record in vivo electrophysiological signals from the cortical surface and the subgaleal space. The devices detect normal physiologic and epileptiform activity, both in acute and chronic recordings. Comparative studies show sensor performance comparable to standard clinical systems and reduced tissue reactivity relative to conventional clinical electrocorticography (ECoG) electrodes. This technology offers general applicability in neural interfaces, with additional potential utility in treatment of disorders where transient monitoring and modulation of physiologic function, implant integrity and tissue recovery or regeneration are required.

Ge (100) and (111) N- and P-FETs With High Mobility and Low-

In this paper, we demonstrate high-mobility bulk Ge N- and P-FETs with GeON gate dielectric. The highest electron mobility to date in Ge is reported, and two times improvement over universal hole mobility is achieved for Ge P-FETs. For the first time, the effect of surface orientation on Ge mobility is investigated experimentally. A 50% improvement in electron mobility is shown for the (111) substrate orientation compared to the (100) orientation. Carrier scattering mechanisms are studied through low-temperature mobility measurements and interface characterization. The conductance technique is applied at low temperatures for complete mapping of the density of interface traps (Dit) across the Ge bandgap and also close to the band edges. Carrier scattering mechanisms and the distribution of Dit are compared for Ge NMOS and PMOS.

T

Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups in the past. The major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In this paper, mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analysis. High source/drain (S/D) parasitic resistance, inversion charge loss due to trapping in the high-K gate dielectric, and high interface trap density are identified as the mechanisms responsible for Ge NMOS performance degradation. After eliminating the degradation mechanisms, the highest electron mobility in Ge NMOS to date, which is, to the best of our knowledge, ~1.5 times the universal Si mobility, is experimentally demonstrated for the Ge N-MOSFETs fabricated with ozone-oxidation surface passivation and low temperature S/D activation processes.

Mobility Characterization

The highest electron mobility in Ge NMOS to-date, ∼1.5 times the universal Si mobility, is demonstrated experimentally. Gate stack engineered with ozone-oxidation is integrated with low temperature S/D activation to fabricate Ge NMOS. Mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analyses for the first time. High S/D parasitic resistance, inversion charge loss due to trapping, and high interface trap density are identified as the mechanisms responsible for Ge NMOS performance degradation.