Hyundai Park

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.

A fiber-to-chip coupler based on Si/SiON cascaded tapers for Si photonic chips

This paper reports a fiber-to-chip coupler consisting of a silicon inverted taper and a silicon oxynitride (SiON) double stage taper, where the cascaded taper structure enables adiabatic mode transfer between a submicron silicon waveguide and a single mode fiber. The coupler, fabricated by a simplified process, demonstrates an average coupling loss of 3.6 and 4.2 dB for TM and TE polarizations, respectively, with a misalignment tolerance of ± 2.2 µm for 1 dB loss penalty.

Performance improvement in silicon arrayed waveguide grating by suppression of scattering near the boundary of a star coupler

We investigate the reduction of transition loss across the star coupler boundary in a silicon arrayed waveguide grating (AWG) by suppressing multimode generation and scattering near the boundary of a star coupler. Eight-channel silicon AWGs were designed with optimal conditions based on enhanced field matching in combination with ultrashallow etched structures. The fabricated AWG demonstrates an insertion loss down to 0.63 dB with a cross talk of -23 to -25.3 dB, exhibiting ~0.8 dB improvement of insertion loss and ~4 dB improvement of cross talk compared to the Si AWG fabricated with a conventional double-etch technique.

Device characterization of the VCSEL-on-silicon as an on chip light source

Advancement of silicon photonics technology can offer a new dimension in data communications with un-precedent bandwidth. Increasing the integration level in the silicon photonics is required to develop compact high-performance chip-level optical interconnects for future systems. Especially, monolithic integration of light source on a silicon wafer is important for future silicon photonic integrated circuits, since realizing a compact on-chip light source on a silicon wafer is a serious issue which impedes practical implementation of the silicon photonic interconnects. At present, due to the lack of a practical light source based on Group IV elements, flip chip-bonded or packaged lasers based on III–V semiconductor are usually being used as external light sources, to feed silicon modulators on SOI wafers to complete a photonic transmitter, except the reported silicon hybrid lasers monolithic-integrated on SOI wafers. To overcome above problem, we have proposed a compact on-chip light source, the directly monolithic-integrated VCSEL on a bulk silicon wafer (VCSEL-on-Si), based on the transplanted epitaxial film by substrate lift-off process and following device-fabrication on the bulk Si wafer. This can offer practical low-power-consumption light sources integrated on a silicon wafer, which can provide a complete chip-level I/O set when combined with monolithic-integrated vertical-illumination Ge-on-Si photodetectors on the same silicon wafer. In this work, we report the characterization of direct-modulation VCSELs-on-Si for λ ~850 nm with CW optical output power > ~2 mW and the threshold current < ~3 mA, over 10 Gb/s operations. We also discuss about the thermal characteristics of the VCSELs-on-Si.

Silicon photonic devices based on SOI/bulk-silicon platforms for chip-level optical interconnects

Based on either a SOI wafer or a bulk-silicon wafer, we discuss silicon photonic devices and integrations for chip-level optical interconnects. We present the low-voltage silicon PICs on a SOI wafer, where Si modulators and Ge-on-Si photodetectors are monolithically-integrated for intra-chip or inter-chip interconnects over 40 Gb/s. For future chip-level integration, the 50 Gb/s small-sized depletion-type MZ modulator with the vertically-dipped PN-depletion-junction (VDJ) is also presented. We report vertical-illumination-type Ge photodetectors on bulk-silicon wafers, with high performances up to 50 Gb/s. We present the bulk-silicon platform for practical implementation of chip-level interconnects, and the performance of the photonic transceiver silicon chip.

Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

Improved performance of a silicon arrayed waveguide grating by reduction of higher order mode generation near the boundary of a star coupler

We investigate the improvement of an insertion loss in silicon arrayed waveguide grating (AWG), by analyzing the multimode generation due to the field-mismatching effect. 8 channel silicon AWGs on a 6” SOI wafer are fabricated with an ultra-shallow etching structure and various aperture size of arrayed WGs. Our experimental results demonstrate the improved insertion loss and crosstalk characteristics. The fabricated AWG shows an insertion loss less than 1 dB with a crosstalk of -23.2 ~ -25.6 dB, exhibiting ~2.5 dB improvement of insertion loss and ~5 dB improvement of crosstalk, compared to our reported result.