Hyung Beom Jang

The impact of liquid cooling on 3D multi-core processors

Recently, 3D integration has been regarded as one of the most promising techniques due to its abilities of reducing global wire lengths and lowering power consumption. However, 3D integrated processors inevitably cause higher power density and lower thermal conductivity, since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Without an efficient cooling method inside the package, 3D integrated processors should suffer severe performance degradation by dynamic thermal management as well as reliability problems. In this paper, we analyze the impact of the liquid cooling on a 3D multi-core processor compared to the conventional air cooling. We also evaluate the leakage power consumption and the lifetime reliability depending on the temperature of each functional unit in the 3D multi-core processor. The simulation results show that the liquid cooling reduces the temperature of the L1 instruction cache (the hottest block in this evaluation) by as much as 45 degrees, resulting in 12.8% leakage reduction, on average, compared to the conventional air cooling. Moreover, the reduced temperature of the L1 instruction cache also improves the reliability of electromigration, stress migration, time-dependent dielectric breakdown, thermal cycling, and negative bias temperature instability significantly.

Exploiting Application/System-Dependent Ambient Temperature for Accurate Microarchitectural Simulation

In the early design stage of processors, Dynamic Thermal Management (DTM) schemes should be evaluated to avoid excessively high temperature, while minimizing performance overhead. In this paper, we show that conventional thermal simulations using the fixed ambient temperature may lead to the wrong conclusions in terms of temperature, performance, reliability, and leakage power. Though ambient temperature converges to a steady-state value after hundreds of seconds when we run SPEC CPU2000 benchmark suite, the steady-state ambient temperature is significantly different depending on applications and system configuration. To overcome inaccuracy of conventional thermal simulations, we propose that microarchitectural thermal simulations should exploit application/system-dependent ambient temperature. Our evaluation results reveal that performance, thermal behavior, reliability, and leakage power of the same DTM scheme are different when we use the application/system-dependent ambient temperature instead of the fixed ambient temperature. For accurate simulation results, future microarchitectural thermal researchers are expected to evaluate their proposed DTM schemes based on application/system-dependent ambient temperature.

Leveraging Process Variation for Performance and Energy: In the Perspective of Overclocking

Process variation is one of the most important factors to be considered in recent microprocessor design, since it negatively affects performance, power, and yield of microprocessors. However, by leveraging process variation, overclocking techniques can improve performance. As microprocessors have substantial clock cycle time margin for yield, there is enough room for performance improvement by overclocking techniques. In this paper, we adopt the F-overclocking technique, which increases clock frequency without changing supply voltage. Our experimental results show that the F-overclocking technique significantly improves performance as well as energy consumption. In addition, the F-overclocking technique is superior to the conventional overclocking technique which increases clock frequency and supply voltage together in the perspective of energy efficiency and reliability, showing similar performance improvement. Furthermore, we propose an adaptive overclocking controller which dynamically applies the F-overclocking technique based on the application characteristics. By adopting our adaptive overclocking controller, we further minimize the reliability loss caused by the F-overclocking technique.

Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay

Most modern microprocessors have multi-level on-chip caches with multi-megabyte shared last-level cache (LLC). By using multi-level cache hierarchy, the whole size of on-chip caches becomes larger. The increased cache size causes the leakage power and area of the on-chip caches to increase. Recently, to reduce the leakage power and area of the SRAM based cache, the SRAM-eDRAM hybrid cache was proposed. For SRAM-eDRAM hybrid caches, however, there has not been any study to analyze the effects of the reduced area on wire delay, cache access time, and performance. By replacing half (or three fourth) of SRAM cells by small eDRAM cells for the SRAM-eDRAM hybrid caches, wire length is shortened, which eventually results in the reduction of wire delay and cache access time. In this paper, we evaluate the SRAM-eDRAM hybrid caches in terms of the energy, area, wire delay, access time, and performance. We show that the SRAM-eDRAM hybrid cache reduces the energy consumption, area, wire delay, and SRAM array access time by up to 53.9%, 49.9%, 50.4%, and 38.7%, respectively, compared to the SRAM based cache.

Intelligent governor for low-power mobile application processors

This paper introduces the power management schemes that control DVFS (Dynamic Voltage and Frequency Scaling) and core shutdown considering the characteristics of an application for the commercial application processors. Most power management schemes used in commercial application processors only monitor the CPU utilization to adjust the CPU frequency. Since recent application processors adopt multi-core CPU, the power management scheme, such as Hotplug, is necessary to manage the power state of the cores. However, none of the schemes mentioned above looks into the application characteristics for the power management. In this paper, we show that considering application characteristics is more beneficial for power management of recent commercial application processors.

Exploiting application-dependent ambient temperature for accurate architectural simulation

In the early stage of processor design, Dynamic Thermal Management (DTM) schemes should be evaluated to avoid excessively high temperature, while minimizing performance overhead as small as possible. In this paper, we show that conventional thermal simulations using fixed ambient temperature may lead to wrong conclusion in terms of performance and temperature; though ambient temperature converges to a steady state after hundreds of seconds, the steady state ambient temperature is significantly different depending on applications. To overcome the inaccuracy of conventional thermal simulations, we propose that architectural thermal simulation should exploit application-dependent ambient temperature. Our evaluation results show that the performance of the same DTM scheme is different, when application-dependent ambient temperature (compared to fixed temperature) is used. For accurate simulation, future architectural thermal researchers are expected to evaluate their proposed DTM schemes, reflecting application- dependent ambient temperature.

Reliable Cache Memory Design for Sensor Networks

With the advance of processor technology, critical device parameters are significantly affected by the process variation. Subsequently, these critical parameters result in high access latencies, significant leakage power and abnormal high temperature. Cache memory circuits are easily affected by the process variation than any other hardware components; due to the densely tied transistors. Moreover, the process variation decreases both the yield of the chip and the lifetime of cache memory used in resource limited devices. Cache memory used in resource limited devices may get affected easily by the process variation due to hostile environments.In this paper, we introduce a simple but very effective process variation tolerant technique using the conventional cache replacement policies. This technique selects the cache block replacement victims excluding the affected cache block by the process variation. Without additional hardware components, the proposed technique can handle the affected cache block minimizing the performance loss. Our experiments show that when we adopted our proposed idea, the performance penalty is less than 1% in case of 12.5% cache blocks cannot be used. Under the severe process variation, our proposed idea deteriorates the performance by only about 2%. By applying our technique in cache memory of resource limited devices, sensor nodes used in sensor networks will be more reliable.

A Trace Cache with DVFS Techniques for a Low Power Microprocessor

The trace cache is a solution to achieving high instruction fetches bandwidth by buffering and reusing dynamic instruction traces. This work presents a new trace cache implementation that includes the DVFS (Dynamic Voltage and Frequency Scaling) techniques for energy efficiency. The focus of this paper is to compare the trace cache with DVFS techniques to the conventional trace cache organization where any DVFS technique is not applied.Instead of storing the basic blocks in the unified trace cache space, the first block of each trace is stored in the specific space of the trace cache and the other basic blocks are stored in the rest of the trace cache space. The first basic block area is not voltage scaled because the first basic block should be supplied to processorpsilas front-end as soon as possible. On the other hand, other basic block area is voltage-scaled down in order to reduce the power consumption. Transistor switching speed of other basic block area is slower than that of the first basic block area due to the lowered supply voltage.Our experiments show that when we adopted the DVFS techniques to the conventional trace cache, 12.8% fetch engine energy consumption is reduced, on average. Applying different supply voltages to each different region of the trace cache, we can reduce the dynamic power consumption. However, we can know that the region which is supplied with lowered voltage inevitably deteriorates the performance of the trace cache by 5.7%.

Quantifying architectural impact of liquid cooling for 3D multi-core processors

For future multi-core processors, 3D integration is regarded as one of the most promising techniques since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Conventional air cooling schemes are not enough for 3D multi-core processors due to the limit of the heat dissipation capability. Without more efficient cooling methods such as liquid cooling, the performance of 3D multi-core processors should be degraded by dynamic thermal management. In this paper, we examine the architectural impact of cooling methods on the 3D multi-core processor to find potential benefits of liquid cooling. We first investigate the thermal behavior and compare the performance of two different cooling schemes. We also evaluate the leakage power consumption and lifetime reliability depending on the temperature in the 3D multi-core processor.

Display Power Management That Detects User Intent

In a proposed display power-management scheme, the laptop detects when the user is not looking at the screen, boosting low-power operation to 50 percent and increasing energy savings by up to 13 percent. With the growth of ubiquitous computing has come an increased reliance on laptops over desktops, and display power management (DPM) that prolongs battery life continues to be a critical issue in maintaining that trend.