Hyung-Joun Yoo

A CMOS Transceiver for a Multistandard 13.56-MHz RFID Reader SoC

A CMOS transceiver for a multistandard 13.56-MHz radio-frequency identification reader system-on-a-chip (SoC) is designed and fabricated. The SoC consists of an RF/analog part for modulation/demodulation and a digital part for controlling the transceiver functionality. Prior to designing the integrated circuit, pre-experiments using discrete components and commercial tags are performed. With the results, overall functions and specifications are determined. For supporting multistandard, several blocks are designed with digital controls according to the standards. In the transmitter, a digitally controlled amplitude modulator for various modulation indexes and a power control circuit are adopted. In the receiver, a variable gain amplifier and a level-controllable comparator, which are also controlled digitally according to the standard, are introduced. The full transceiver SoC is implemented in the Chartered 0.18-¿m CMOS technology. The measurement results of the implemented chip indicate that the designed transceiver operates in a multistandard mode.

A 5.8-GHz High-Frequency Resolution Digitally Controlled Oscillator Using the Difference Between Inversion and Accumulation Mode Capacitance of pMOS Varactors

This paper proposes an oppositely coupled varactor pair and reports the measured results for applying to a test digitally controlled oscillator (DCO). The pair exploits the differences between the accumulation region capacitance and inversion region capacitance of pMOS varactors. The novel varactor pairs provide much smaller switchable capacitances than those of other approaches, and hence, the test DCO for verifying the property of the pair achieves the high-frequency resolution. The pairs and test DCO are implemented in a 0.18-μm CMOS process. The switchable discrete capacitance of 32 aF is obtained by using the novel varactor pairs, and the test DCO has a frequency resolution of about 110 kHz at 5.8 GHz. Furthermore, ΔC of 4-aF and 14-kHz frequency resolution can be obtained through the dithering processes. The test DCO achieves a low phase noise of -117.6 dBc/Hz at 1-MHz offset from 5.8 GHz.

A fully digital polar transmitter using a digital-to-time converter for high data rate system

Digital polar transmitter is suitable for high integrated and power efficient implementation. In order to support high data rate communication systems, the digital polar transmitter need a high performance phase modulator with high resolution and sub-nanoseconds settling time. In this paper, as a phase modulator, a digital-to-time converter (DTC) with high resolution and short settling time is proposed. The DTC adopts serial delay architecture, and can be used in high data-rate and gigahertz wireless communication system. It exploits inverters with different delays to generate small phase differences while maintaining the sub-nanoseconds settling time. The DTC implemented in the TSMC 0.18 um CMOS process achieves the phase resolution of 0.78 ps and relative settling time of 0.7 ns with 2.5 GHz clock while consuming 0.8 mW of power.

A 5.9 GHz LC-based digitally controlled oscillator with high frequency resolution using novel varactor pairs

This paper reports an LC-based digitally controlled oscillator (DCO) using novel varactor pairs. Proposed DCO has high frequency resolution with low phase noise in 5.9 GHz. The DCO exploits the difference between the accumulation region capacitance and inversion region capacitance of two PMOS varactors. The novel varactor pairs make much smaller switchable capacitance than those of other approaches, and hence the DCO achieves the high frequency resolution and low phase noise. Also, identical sizes of PMOS varactor make them robust from process variation. The DCO implemented in 0.18 um CMOS process operates from 5.7 GHz to 6.3 GHz with 14 kHz frequency resolution which indicates the unit switchable capacitance of 3.5 aF. The designed DCO achieves a low phase-noise of −117 dBc/Hz at 1 MHz offset.

A 0.7-MHz–10-MHz

A hybrid baseband chain for Long-Term Evolution (LTE) was implemented in a TSMC 65-nm CMOS process. It has an active area of 0.75 mm2 and a power consumption of 10.8 mW at a supply of 1.8 V. The proposed baseband chain consists of a continuous-time (CT) lowpass filter and a charge-domain discrete-time (DT) filter with a variable gain amplifier (VGA) and a DC-offset canceller (DCOC). The passband distortion of the DT filter is calibrated by varying the quality (Q)-factor of the CT filter, which is easily tuned by switched-resistors. The charge-domain DT filter is adopted for anti-aliasing filtering and efficient interferer rejection with small size and low power consumption. By combining the CT and the DT filters, the baseband chain acquires improved passband flatness with an in-band ripple of less than 1 dB from 0.7 MHz to 10 MHz. It also has a gain of 50.8 dB, input-referred noise of 22.8 nV/√Hz, and an out-of-band IIP3 of 29 dBm.

{\rm CT}+{\rm DT}

This paper proposes a low-power polar demodulator for electrical impedance spectroscopy. The magnitude and phase of impedance are measured by a novel sampling scheme and an XOR-based scheme, respectively. The novel sampling scheme only requires switched capacitor circuits and clock signals that are already used in the analog-to-digital conversion and the phase measurement. Since the proposed demodulator does not require any additional circuits for the magnitude measurement, low power consumption and small die areas can be achieved. The proposed demodulator designed using a 0.18-μm CMOS process consumes about 10-mW average power with 0.23-mm2 active area.

Hybrid Baseband Chain With Improved Passband Flatness for LTE Application

A charge sampler-based reconfigurable high-order moving-average (MA) filter designed using a temporal MA method is proposed. The proposed filter has a higher gain than conventional MA filters. Moreover, the filter supports variable sizes and orders of MA. That is, the filter has a flexible frequency response by changing not only the sampling frequency but also the MA size (N) and MA order (M). The N and M are easily controlled by changing the clock patterns; therefore, the filter is suitable for multimode transceivers. To minimize the power consumption, inverter-based transconductance amplifiers are used. Here, our fabricated filter using a 65-nm CMOS technology supports MA (N = 2, M = 3) and MA (N = 3, M = 2) without changing the hardware.

A low-power polar demodulator for impedance spectroscopy based on a novel sampling scheme

A CMOS sinusoidal signal generator based on discrete-time (DT) and continuous-time (CT) processing is proposed for electrical bioimpedance spectroscopy supporting beta dispersion range of tissues. Differential stepwise sine-like signals with oversampling ratio (OSR) of 16 are used for input signals. DT filters with OSR=16 are used to attenuate close-in harmonics of these input signals, and a CT transconductance-C low-pass filter is used to attenuate less suppressed high-order harmonics under the DT processing of OSR=16. This proposed signal generator designed in a 0.25μm CMOS process supports frequency range from 1 kHz to 2.048 MHz. The spurious-free dynamic range more than 65.7 dB and the total harmonic distortion less than 51.6m% were achieved for about 550-mVpp output amplitude.

Reconfigurable High-Order Moving-Average Filter Using Inverter-Based Variable Transconductance Amplifiers

This paper proposes an interface circuit for a three-electrode metal-oxide (MOX) gas sensor. The proposed interface circuit adopts a pulse width modulation (PWM) signal to control the heater and to measure the sensor resistance almost simultaneously. Furthermore, to measure the resistance of the sensing material, our circuit adopts a scheme that works regardless of the asymmetry of the sensor geometry and an opamp-based integrator to provide a wide input dynamic range. Our circuit also introduces an additional noise and offset reduction technique. Therefore, it is highly suitable for accurate data acquisition.

A CMOS sinusoidal signal generator based on mixed-time processing for electrical bioimpedance spectroscopy supporting beta dispersion range

This paper presents a single-chip CMOS multi-standard frequency synthesizer for global system for mobile communications (GSM)/enhanced data rate for GSM evolution (EDGE) and long-term evolution (LTE) applications. Low phase-noise characteristics are achieved both in-band and out-of-band through a voltage-and-digitally controlled oscillator (VDCO) and digital calibration blocks. The proposed hybrid phase-locked loop (PLL) has two feedback loops. One is the main loop of the analog PLL and the other is a digital feedback loop used for polar modulation and digital calibrations. The digital feedback loop, nested inside the PLL, linearizes and accurately controls the tunable characteristic of the VDCO, which is important for the polar modulation. In the GSM/EDGE mode, the PLL has a 0.79 ° root-mean-square (rms) phase error and the measured phase noise is -162.5 dBc/Hz at a 20-MHz offset from an 824-MHz carrier. In the LTE mode, the measured local oscillator rms jitter is 218 fs while the PLL consumes 26.4 mW. The resulting figure of merit of the proposed PLL is -239 dB, which is superior to recent multi-standard PLLs. This multi-standard hybrid PLL is implemented in a 65-nm CMOS technology and occupies 0.72 mm2.