Soon-Jae Kweon

A 0.7-MHz–10-MHz

A hybrid baseband chain for Long-Term Evolution (LTE) was implemented in a TSMC 65-nm CMOS process. It has an active area of 0.75 mm2 and a power consumption of 10.8 mW at a supply of 1.8 V. The proposed baseband chain consists of a continuous-time (CT) lowpass filter and a charge-domain discrete-time (DT) filter with a variable gain amplifier (VGA) and a DC-offset canceller (DCOC). The passband distortion of the DT filter is calibrated by varying the quality (Q)-factor of the CT filter, which is easily tuned by switched-resistors. The charge-domain DT filter is adopted for anti-aliasing filtering and efficient interferer rejection with small size and low power consumption. By combining the CT and the DT filters, the baseband chain acquires improved passband flatness with an in-band ripple of less than 1 dB from 0.7 MHz to 10 MHz. It also has a gain of 50.8 dB, input-referred noise of 22.8 nV/√Hz, and an out-of-band IIP3 of 29 dBm.

{\rm CT}+{\rm DT}

This paper proposes a low-power polar demodulator for electrical impedance spectroscopy. The magnitude and phase of impedance are measured by a novel sampling scheme and an XOR-based scheme, respectively. The novel sampling scheme only requires switched capacitor circuits and clock signals that are already used in the analog-to-digital conversion and the phase measurement. Since the proposed demodulator does not require any additional circuits for the magnitude measurement, low power consumption and small die areas can be achieved. The proposed demodulator designed using a 0.18-μm CMOS process consumes about 10-mW average power with 0.23-mm2 active area.

Hybrid Baseband Chain With Improved Passband Flatness for LTE Application

A charge sampler-based reconfigurable high-order moving-average (MA) filter designed using a temporal MA method is proposed. The proposed filter has a higher gain than conventional MA filters. Moreover, the filter supports variable sizes and orders of MA. That is, the filter has a flexible frequency response by changing not only the sampling frequency but also the MA size (N) and MA order (M). The N and M are easily controlled by changing the clock patterns; therefore, the filter is suitable for multimode transceivers. To minimize the power consumption, inverter-based transconductance amplifiers are used. Here, our fabricated filter using a 65-nm CMOS technology supports MA (N = 2, M = 3) and MA (N = 3, M = 2) without changing the hardware.

A low-power polar demodulator for impedance spectroscopy based on a novel sampling scheme

A CMOS sinusoidal signal generator based on discrete-time (DT) and continuous-time (CT) processing is proposed for electrical bioimpedance spectroscopy supporting beta dispersion range of tissues. Differential stepwise sine-like signals with oversampling ratio (OSR) of 16 are used for input signals. DT filters with OSR=16 are used to attenuate close-in harmonics of these input signals, and a CT transconductance-C low-pass filter is used to attenuate less suppressed high-order harmonics under the DT processing of OSR=16. This proposed signal generator designed in a 0.25μm CMOS process supports frequency range from 1 kHz to 2.048 MHz. The spurious-free dynamic range more than 65.7 dB and the total harmonic distortion less than 51.6m% were achieved for about 550-mVpp output amplitude.

Reconfigurable High-Order Moving-Average Filter Using Inverter-Based Variable Transconductance Amplifiers

The proposed sensor interface circuit provides an integrative baseline/offset compensation to give higher adaptability and effectiveness for multiparameter sensing microsystems. Capacitive/resistive and voltage type sensors are dealt with and switched-capacitor-based circuits are mostly employed to facilitate integrative baseline/offset cancellation and interface various types of sensors. For integrative signal conditioning, sensor signals are first converted to voltage signals and then given rail-to-rail baseline compensation and fine offset cancellation of 0.7 mV/bit. At the same time, each interface circuit demonstrates a large total conversion gain (C: 194 mV/fF, R: 6260 mV/k

A CMOS sinusoidal signal generator based on mixed-time processing for electrical bioimpedance spectroscopy supporting beta dispersion range

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Multiparameter Sensor Interface Circuit With Integrative Baseline/Offset Compensation by Switched-Capacitor Level Shifting/Balancing

, V: 230 V/V) and a coefficient of determination (R2) over 0.998, which indicates a high conversion linearity.

A CMOS low-power polar demodulator for electrical bioimpedance spectroscopy using adaptive self-sampling schemes

A CMOS integrated low-power polar demodulator for electrical bioimpedance spectroscopy is proposed. This polar demodulator extracts magnitude and phase of tissues impedance. Two adaptive self-sampling schemes, namely zero-time sampling (ZTS) and peak-time sampling (PTS), are proposed to efficiently extract the magnitude of impedance. Since ZTS scheme reuses clock signals used in the XOR-based phase-extracting circuit, low-power consumption is achieved. When ZTS scheme is used, magnitude error increases as frequency of the injected sinusoidal signal increases. Instead of ZTS scheme, PTS scheme is used when the signal above 100 kHz is injected. Targeting 1-kHz to 2.048-MHz frequency range, the proposed demodulator designed in a 0.25-im CMOS process consumes 10.3 mW at its maximum with magnitude and phase errors of 1.0% and 1.3°, respectively.

A discrete-time channel-selection filter with flat passband characteristic for LTE

A discrete-time channel-selection filter with flat passband characteristic that satisfies the LTE specification is proposed. To improve the flatness in passband, a second order IIR filter and a compensation filter are adopted. High stopband attenuation is achieved by using the moving average filters. Through the control of sampling frequency, the proposed discrete-time filter chain satisfies the required specifications for all the channels in LTE. The filter is implemented using TSMC 65-nm CMOS process. The simulation shows that proposed discrete-time filter chain has flatness degradation lower than about 4 dB at passband edge.

A reconfigurable time-to-digital converter based on time stretcher and chain-delay-line for electrical bioimpedance spectroscopy

We propose a time-to-digital converter (TDC) with a reconfigurable time resolution from 0.1 ns to 244 ns using a low-speed reference clock of 32.768 MHz. This TDC combines a coarse counter with two parallel fine TDCs which measure front and back fractional times of the coarse counter. In order to obtain high precision without increasing the reference clock speed, the fractional times are stretched through time stretchers of two fine stages with tunable stretching factor and are quantized through fine counters and chain-delay-lines. The time resolution is tuned by controlling the counting clock speed or the stretching factor. The designed TDC in a 0.18-μm CMOS process quantizes a phase of impedance with less than 0.088° error for frequency range from 1 kHz to 2048 kHz. As the result, this TDC is suitable for phase quantizers in bioimpedance spectrometers.