Yong-Chang Choi

A CMOS Transceiver for a Multistandard 13.56-MHz RFID Reader SoC

A CMOS transceiver for a multistandard 13.56-MHz radio-frequency identification reader system-on-a-chip (SoC) is designed and fabricated. The SoC consists of an RF/analog part for modulation/demodulation and a digital part for controlling the transceiver functionality. Prior to designing the integrated circuit, pre-experiments using discrete components and commercial tags are performed. With the results, overall functions and specifications are determined. For supporting multistandard, several blocks are designed with digital controls according to the standards. In the transmitter, a digitally controlled amplitude modulator for various modulation indexes and a power control circuit are adopted. In the receiver, a variable gain amplifier and a level-controllable comparator, which are also controlled digitally according to the standard, are introduced. The full transceiver SoC is implemented in the Chartered 0.18-¿m CMOS technology. The measurement results of the implemented chip indicate that the designed transceiver operates in a multistandard mode.

A 5.8-GHz High-Frequency Resolution Digitally Controlled Oscillator Using the Difference Between Inversion and Accumulation Mode Capacitance of pMOS Varactors

This paper proposes an oppositely coupled varactor pair and reports the measured results for applying to a test digitally controlled oscillator (DCO). The pair exploits the differences between the accumulation region capacitance and inversion region capacitance of pMOS varactors. The novel varactor pairs provide much smaller switchable capacitances than those of other approaches, and hence, the test DCO for verifying the property of the pair achieves the high-frequency resolution. The pairs and test DCO are implemented in a 0.18-μm CMOS process. The switchable discrete capacitance of 32 aF is obtained by using the novel varactor pairs, and the test DCO has a frequency resolution of about 110 kHz at 5.8 GHz. Furthermore, ΔC of 4-aF and 14-kHz frequency resolution can be obtained through the dithering processes. The test DCO achieves a low phase noise of -117.6 dBc/Hz at 1-MHz offset from 5.8 GHz.

A fully digital polar transmitter using a digital-to-time converter for high data rate system

Digital polar transmitter is suitable for high integrated and power efficient implementation. In order to support high data rate communication systems, the digital polar transmitter need a high performance phase modulator with high resolution and sub-nanoseconds settling time. In this paper, as a phase modulator, a digital-to-time converter (DTC) with high resolution and short settling time is proposed. The DTC adopts serial delay architecture, and can be used in high data-rate and gigahertz wireless communication system. It exploits inverters with different delays to generate small phase differences while maintaining the sub-nanoseconds settling time. The DTC implemented in the TSMC 0.18 um CMOS process achieves the phase resolution of 0.78 ps and relative settling time of 0.7 ns with 2.5 GHz clock while consuming 0.8 mW of power.

A 5.9 GHz LC-based digitally controlled oscillator with high frequency resolution using novel varactor pairs

This paper reports an LC-based digitally controlled oscillator (DCO) using novel varactor pairs. Proposed DCO has high frequency resolution with low phase noise in 5.9 GHz. The DCO exploits the difference between the accumulation region capacitance and inversion region capacitance of two PMOS varactors. The novel varactor pairs make much smaller switchable capacitance than those of other approaches, and hence the DCO achieves the high frequency resolution and low phase noise. Also, identical sizes of PMOS varactor make them robust from process variation. The DCO implemented in 0.18 um CMOS process operates from 5.7 GHz to 6.3 GHz with 14 kHz frequency resolution which indicates the unit switchable capacitance of 3.5 aF. The designed DCO achieves a low phase-noise of −117 dBc/Hz at 1 MHz offset.

A 0.7-MHz–10-MHz

A hybrid baseband chain for Long-Term Evolution (LTE) was implemented in a TSMC 65-nm CMOS process. It has an active area of 0.75 mm2 and a power consumption of 10.8 mW at a supply of 1.8 V. The proposed baseband chain consists of a continuous-time (CT) lowpass filter and a charge-domain discrete-time (DT) filter with a variable gain amplifier (VGA) and a DC-offset canceller (DCOC). The passband distortion of the DT filter is calibrated by varying the quality (Q)-factor of the CT filter, which is easily tuned by switched-resistors. The charge-domain DT filter is adopted for anti-aliasing filtering and efficient interferer rejection with small size and low power consumption. By combining the CT and the DT filters, the baseband chain acquires improved passband flatness with an in-band ripple of less than 1 dB from 0.7 MHz to 10 MHz. It also has a gain of 50.8 dB, input-referred noise of 22.8 nV/√Hz, and an out-of-band IIP3 of 29 dBm.

{\rm CT}+{\rm DT}

This paper presents a single-chip CMOS multi-standard frequency synthesizer for global system for mobile communications (GSM)/enhanced data rate for GSM evolution (EDGE) and long-term evolution (LTE) applications. Low phase-noise characteristics are achieved both in-band and out-of-band through a voltage-and-digitally controlled oscillator (VDCO) and digital calibration blocks. The proposed hybrid phase-locked loop (PLL) has two feedback loops. One is the main loop of the analog PLL and the other is a digital feedback loop used for polar modulation and digital calibrations. The digital feedback loop, nested inside the PLL, linearizes and accurately controls the tunable characteristic of the VDCO, which is important for the polar modulation. In the GSM/EDGE mode, the PLL has a 0.79 ° root-mean-square (rms) phase error and the measured phase noise is -162.5 dBc/Hz at a 20-MHz offset from an 824-MHz carrier. In the LTE mode, the measured local oscillator rms jitter is 218 fs while the PLL consumes 26.4 mW. The resulting figure of merit of the proposed PLL is -239 dB, which is superior to recent multi-standard PLLs. This multi-standard hybrid PLL is implemented in a 65-nm CMOS technology and occupies 0.72 mm2.

Hybrid Baseband Chain With Improved Passband Flatness for LTE Application

A HF (13.56 MHz) RFID receiver architecture SoC (System on Chip) is proposed. The receiver can be used in the standards of ISO/IEC 14443 type A/B, 15693, and 18000-3. Before designing the circuit, standard analysis is processed. And also, we did a previous measurement for preparing implementation as a chip level. That is, a RFID transceiver test board using commercial components was configured and tested. Through the board experiments, we checked the possibilities of operation of designed receiver. Based on the experiment results, the multi-standard 13.56 MHz RFID receiver SoC was designed and fabricated using TSMC 0.18 um CMOS technology. The test results show that designed receiver system as a chip level can be operated properly in multiple standard conditions.

Multi-Standard Hybrid PLL With Low Phase-Noise Characteristics for GSM/EDGE and LTE Applications

We analyzed 13.56 MHz RFID standards and obtained specifications of transmitting section and receiving section of the RFID reader. With these analyses, we proposed a multistandard 13.56 MHz RFID reader system. For supporting multistandard in 13.56 MHz RFID system, circuits for controlling modulation index and power emitted to the tag are added in transmitter. In order to accept to various response signal levels from the tag, a certain voltage is applied to the receiver after eliminating DC voltage at VGA input and internal reference voltage is set in comparator. From measurement using commercial tags and additional FPGA board, we can conclude that this transceiver chip is compatible with mentioned standards.

A 13.56MHz receiver SoC for multi-standard RFID reader

High resolution capacitance-to-digital converters (CDC) usually have severe capacitance range limitations or high power consumption. This paper presents a power detection based 16-bit CDC with a maximum capacitance range superior to 1 nF and a capacitance resolution as small as 0.27 fF. This works multi-stage power detector provides the CDC with three different sensitivity rates making it highly versatile. An on-chip low-pass filter was added to prove the methods reliability for on-chip applications. The circuit was designed using a 0.25-μm CMOS technology, operates at a single 2.5-V supply, and consumes less than 1.86 mW.

An analog front-end for 13.56 MHz multi-standard RFID system

Summary form only given. This paper presents a direct conversion Korean standard T-DMB SoC tuner using a 65nm low power CMOS technology with the best feature of size, power and BoM ever reported. A digital F/E enhanced function is implemented to reduce analog signal processing empowered by oversampled A/D converter, digital channel selection filter and lots of digital calibration blocks. And the designed LNA excludes all required inductors. Thus high voltage gain and low current consumption are achieved due to their high Q factor. A single-to-differential signaling down-conversion mixer is also announced which has well balanced output characteristic. A DC/DC converter is adopted as well for the further low power consuming. The tunable clock frequency scheme of DC/DC buck converter can prevent a degradation of sensitivity performances which is planed value to escape the channel center frequency. This reported SoC tuner consumes only 28mA at maximum gain mode. And -103.5dBm of sensitivity and 48dBc of N±1 adjacent-channel selectivity are achieved also with only 5 external LC components. This SoC occupies 2.5×2.5mm2 die and WLCSP chip size.