Hyung-Shin Kwon

Analysis of dynamic retention characteristics of NWL scheme in high density DRAM

A Negative Word Line (NWL) bias scheme is an effective method to reduce the junction leakage current of DRAM cell transistor by reducing the channel implantation dose used to adjust the threshold voltage. However, the static data retention characteristics might be degraded by the GIDL current due to increasing E-filed between the gate and the drain in off-state. In addition, it could cause degradation of the dynamic data retention characteristics by occurring negative word line bias (VNWL) fluctuation during DRAM chip operation, because of increase of the sub-threshold leakage current of cell transistor. This paper gives a detailed analysis of the problem on the dynamic chip test in NWL scheme, especially for the Refresh Cycle Reduction (RCR) mode test and suggests the design guideline for the chip test.

A novel 0.79 /spl mu/m/sup 2/ SRAM cell by KrF lithography and high performance 90 nm CMOS technology for ultra high speed SRAM

The smallest SRAM cell, 0.79 /spl mu/m/sup 2/, was realized by a revolutionary cell layout, fine tuned OPC technique to overcome the 248 nm KrF lithography limitation, instead of using 193 nm ArF lithography. Sub-100 nm CMOS technology was indispensable to achieve the cell size as well as the performance. The high performance transistors were made with 80 nm gate length including 15 /spl Aring/ nitrided gate oxide layer, indium channel and halo implantation processes. The novel cell exhibits excellent neutron SER immunity, compared with ones of the SRAM cell by previous generation technologies.

Suppression of CoSix Induced Leakage Current Using Novel Capping Process for Sub-0.10um node SRAM Cell Technology

We present a novel capping process for sub-0.10um node SRAM cell to suppress the Co silicide induced leakage current. The dimensions in the SRAM cell are scaled down to sub-0.10um. As a result, the CoSix induced leakage current increases as the sizes of the contact and the active area decrease due to the CoSix defects and the contact etch induced CoSix pitting. The double stacked layers on Co silicide successfully reduced the junction leakage current and widened the borderless contact etching process window by suppression of the CoSix defects and the Co silicide pittings.