Sung-Bong Kim

A 14 nm FinFET 128 Mb SRAM With V

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 μm2 and a 0.080 μm2 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve VMIN of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the VMIN of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 VMIN with 200 mV improvement by NBL, and 0.47 VMIN for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved VMIN reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

_{\rm MIN}

Ta/sub 2/O/sub 5/ dielectric on poly-Si cylinder capacitors, chemical-mechanical polishing (CMP) planarization, pure W bit-line, and Al reflow were integrated into a highly manufacturable DRAM process technology. This technology provided larger process margin, higher reliability, and better design flexibility. In addition, the critical steps of the new process has been reduced by 25% of those of the conventional process. The manufacturability of the technology has been proven by applying it to 16 Mbit density DRAMs with 256 Mbit design rule (0.28 /spl mu/m).<<ETX>>

Enhancement Techniques for Low-Power Applications

The power consumption of a mobile application processor (AP) is strongly limited by the SRAM minimum operating voltage, VMIN [1], since the 6T bit cell must balance between write-ability and bit cell stability. However, the SRAM VMIN scales down gradually with advanced process nodes due to increased variability. This is evident with the quantized device-width and limited process-knobs of a FinFET technology, which has greatly affected SRAM design [2-4]. Therefore, assist-circuits are more crucial in a FinFET technology to improve VMIN, which in turn adds to the Power, Performance, and Area (PPA) gain of SRAM.

Highly manufacturable process technology for reliable 256 Mbit and 1 Gbit DRAMs

With the explosive growth of battery-operated portable devices, the demand for low power and small size has been increasing for system-on-a-chip (SoC). The FinFET is considered as one of the most promising technologies for future low-power mobile applications because of its good scaling ability, high on-current, better SCE and subthreshold slope, and small leakage current [1]. As a key approach for low-power, supply-voltage (VDD) scaling has been widely used in SoC design. However, SRAM is the limiting factor of voltage-scaling, since all SRAM functions of read, write, and hold-stability are highly influenced by increased variations at low VDD, resulting in lower yield. In addition, the width-quantization property of FinFET device reduces the design window for transistor sizing, and increases the failure probability due to the un-optimized bitcell sizing [1]. In order to overcome the bitcell challenges to high yield, peripheral-assist techniques are required. In this paper, we present 14nm FinFET-based 128Mb 6T SRAM chips featuring low-VMIN with newly developed assist techniques.

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization

The smallest SRAM cell, 0.79 /spl mu/m/sup 2/, was realized by a revolutionary cell layout, fine tuned OPC technique to overcome the 248 nm KrF lithography limitation, instead of using 193 nm ArF lithography. Sub-100 nm CMOS technology was indispensable to achieve the cell size as well as the performance. The high performance transistors were made with 80 nm gate length including 15 /spl Aring/ nitrided gate oxide layer, indium channel and halo implantation processes. The novel cell exhibits excellent neutron SER immunity, compared with ones of the SRAM cell by previous generation technologies.

13.2 A 14nm FinFET 128Mb 6T SRAM with V MIN -enhancement techniques for low-power applications

We have developed a 1.29 um2 full CMOS SRAM cell for low power applications, which is the world-smallest one by using 0.12 um single gate CMOS technology and optical enhancement techniques for extending use of 248 nm KrF lithography. It includes (1) 0.28 um pitch contacts formed by aerial image controlled patterns on phase shift mask (PSM) and photo resist flow, (2) gate patterns with 0.24 um pitch, (3) 0.13 um buried channel pMOS, and (4) spacer-on-stopper (SOS) MOSFET structure for expanding contact area and reducing band-to-band tunneling leakage.