Jong-Hyoung Lim

A Prevenient Voltage Stress Test Method for High Density Memory

The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).

Analysis of dynamic retention characteristics of NWL scheme in high density DRAM

A Negative Word Line (NWL) bias scheme is an effective method to reduce the junction leakage current of DRAM cell transistor by reducing the channel implantation dose used to adjust the threshold voltage. However, the static data retention characteristics might be degraded by the GIDL current due to increasing E-filed between the gate and the drain in off-state. In addition, it could cause degradation of the dynamic data retention characteristics by occurring negative word line bias (VNWL) fluctuation during DRAM chip operation, because of increase of the sub-threshold leakage current of cell transistor. This paper gives a detailed analysis of the problem on the dynamic chip test in NWL scheme, especially for the Refresh Cycle Reduction (RCR) mode test and suggests the design guideline for the chip test.

A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method

Screening latent defects in a wafer test process is very important task in both reducing memory manufacturing cost and enhancing the reliability of emerging package products such as SIP, MCP, and WSP. In terms of the package assembly cost, these package products are required to adopt the KGD (known good die) quality level. However, the KGD requires a long burn-in time, added testing time, and high cost equipments. To alleviate these problems, this paper presents a statistical wafer burn-in methodology for the latent defect screen in the wafer test process. The newly proposed methodology consists of a defect-based wafer burn-in (DB-WBI) stress method based on DRAM operation characteristics and a statistical stress optimization method using RSM (response surface method) on the DRAM manufacturing test process. Experimental data shows that package test yields in the immature fabrication process improved by up to 6%. In addition, experimental results show that the proposed methodology can guarantee reliability requirements with a shortened package burn-in time. In conclusion, this methodology realizes a simplified manufacturing test process supporting time to market with high reliability.