Hyungdong Roh

A 0.9-V 60-

A 0.9-V 60-muW delta-sigma modulator is designed using standard CMOS 0.13-mum technology. The modulator achieves 83-dB dynamic range in a signal bandwidth of 20 kHz with a sampling frequency of 2 MHz. The input-feedforward architecture is used to reduce the voltage swing of the integrators, which enables low-power amplifiers. By considering the characteristics of the modulator architecture, low-quiescent operational transconductance amplifiers are designed, which use positive feedback to increase dc gain. The designed modulator shows very high figure of merit among the state-of-the-art sub-l-V modulators.

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We present the design of a single-chip delta-sigma (DeltaSigma) modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates output pulse signals using a single-bit fourth-order high-performance DeltaSigma modulator. To achieve a high signal-to-noise ratio and ensure system stability for a large input range, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard 0.18-mum CMOS process. The active area of the chip is 1.6 mm2. It operates for the signal bandwidth from 20 Hz to 20 kHz. The measured total harmonic distortion plus noise at the 32-Omega load terminal is 0.022% from a single 3-V power supply.

1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range

A 0.6-V 34-muW delta-sigma modulator implemented by using a standard 0.13-mum complementary metal-oxide-semiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order delta-sigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 muW for the modulator, and the core chip size is 0.33 mm2 .

Class-D Audio Amplifier Using 1-Bit Fourth-Order Delta-Sigma Modulation

A fourth-order single-bit delta-sigma modulator is presented for sensor applications. The loop filter is composed of both feedback and feedforward paths, and the modulator is implemented using fully differential switched-capacitor techniques. A test chip was fabricated in a 0.18-mum standard complementary metal-oxide semiconductor (CMOS) process. The chip core area is 1.22 mm2, and its power consumption is 5.6 mW from a 3.0-V power supply. Measurement results show that a maximum 99-dB dynamic range is achievable at a clock rate of 3.2 MHz for the 20-kHz bandwidth. The designed chip is targeted for high-accuracy and wide-bandwidth sensor applications such as the resistor-based current sensors and the Hall-effect sensors in motor control systems.

A 0.6-V Delta–Sigma Modulator With Subthreshold-Leakage Suppression Switches

This brief proposes a delta-sigma modulator that operates at extremely low voltage without using a clock boosting technique. To maintain the advantages of a discrete-time integrator in oversampled data converters, a mixed differential difference amplifier (DDA) integrator is developed that removes the input sampling switch in a switched-capacitor integrator. Conventionally, many low-voltage delta-sigma modulators have used high-voltage generating circuits to boost the clock voltage levels. A mixed DDA integrator with both a switched-resistor and a switched-capacitor technique is developed to implement a discrete-time integrator without clock boosted switches. The proposed mixed DDA integrator is demonstrated by a third-order delta-sigma modulator with a feedforward topology. The fabricated modulator shows a 68-dB signal-to-noise-plus-distortion ratio for a 20-kHz signal bandwidth with an oversampling ratio of 80. The chip consumes 140 μW of power at a true 0.4-V power supply, which is the lowest voltage without a clock boosting technique among the state-of-the-art modulators in this signal band.

A 99-dB DR Fourth-Order Delta–Sigma Modulator for 20-kHz Bandwidth Sensor Applications

This paper presents a bufferless interface that can be directly connected to a single-ended capacitive sensor such as an electret condenser microphone. A high-input impedance interface is developed using only a continuous-time loop filter, whereas conventional interface circuits are composed of a buffer, a preamplifier, an antialiasing filter, and a high-order switched-capacitor loop filter. Equipped with an active gm-C integrator, this interface chip is designed to implement all the required functions, i.e., high-input impedance buffering, preamplification, antialiasing filtering, and analog-to-digital conversion. The inherent antialiasing filtering function also provides a significant advantage in terms of silicon areas and power consumption. The complete interface channel achieves a 75-dB dynamic range and a 60.3-dB signal-to-noise-plus-distortion ratio over a 25-kHz signal band, which satisfies the requirements for electret microphones. The power consumption of the interface channel is 600 μW, and the chip dissipates a total of 860 μW from the 3.3-V supply.

A True 0.4-V Delta–Sigma Modulator Using a Mixed DDA Integrator Without Clock Boosted Switches

A 0.6-V, 8-μW bandgap reference without BJTs is realized in the standard CMOS 0.13μm technology. All MOS transistors bandgap reference circuit with very low supply voltage 0.6V is designed. The chopper stabilization technique is used to improve the accuracy of the bandgap reference voltage. The measurement results have confirmed that the chopper stabilization technique reduces bandgap voltage error from 100mV to 30mV comparing to the one without chopper stabilization technique.

A Bufferless Interface for Single-Ended ECM Sensors

Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a fully synthesised digital decimation filter that provides a time-to-market advantage. The filter consists of a cascaded integrator-comb filter and two cascaded half-band FIR filters. A canonical signed-digit representation of the filter coefficients is used to minimise the area and to reduce the hardware complexity of the multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated by using 0.25-μm CMOS technology with an active area of 1.36 mm2 and shows 4.4 mW power consumption at a clock rate of 2.8224 MHz. Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time. This is possible because the filter does not have process-dependent ROM or RAM circuits.

All MOS transistors bandgap reference using chopper stabilization technique

This paper presents the design of a continuous-time delta-sigma (ΔΣ) modulator for acoustic sensor networks. A feed-forward structure without a summing block is used to reduce the power consumption of the ΔΣ modulator. A high-linearity active-RC filter is used to improve the resolution of the ΔΣ modulator. A low-power, high-resolution fourth-order continuous-time ΔΣ modulator with 1-bit quantization was developed by using 0.13-µm, 1-poly 8-metal CMOS technology, with a core area of 0.58 mm². Simulation results show that the modulator achieved 91.3-dB SNDR (signal-to-noise plus distortion ratio) over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating 290 µW of power from a 3.3-V supply.

Fully synthesised decimation filter for delta-sigma A/D converters

In this paper, we present a fourth-order single-bit delta-sigma modulator with wide dynamic range. This modulator is suitable for distributed sensor and audio codec applications. This chip was fabricated in a 0.18- mum one-poly, four-metal CMOS technology, and occupies 1.22-mm2 active area. The circuit is clocked at 3.2 MHz and the overall power consumption is 5.6 mW from a 3.0 V power supply. Experimental results show a maximum dynamic range of 99 dB within a 20- kHz bandwidth.