Jeongjin Roh

A 0.9-V 60-

A 0.9-V 60-muW delta-sigma modulator is designed using standard CMOS 0.13-mum technology. The modulator achieves 83-dB dynamic range in a signal bandwidth of 20 kHz with a sampling frequency of 2 MHz. The input-feedforward architecture is used to reduce the voltage swing of the integrators, which enables low-power amplifiers. By considering the characteristics of the modulator architecture, low-quiescent operational transconductance amplifiers are designed, which use positive feedback to increase dc gain. The designed modulator shows very high figure of merit among the state-of-the-art sub-l-V modulators.

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A new error amplifier is presented for fast transient response of dc-dc converters. The amplifier has low quiescent current to achieve high power conversion efficiency, but it can supply sufficient current during large-signal operation. Two comparators detect large-signal variations, and turn on extra current supplier if necessary. The amount of extra current is well controlled, so that the system stability can be guaranteed in various operating conditions. The simulation results show that the new error amplifier achieves significant improvement in transient response than the conventional one.

1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range

A high-voltage-tolerant buck converter with a novel adaptive power transistor driver is proposed in this paper. In order to minimize the RON of the cascode power transistor, the proposed scheme uses optimized and separated driving voltages for bias of the pMOS and nMOS power transistors. This increases not only the conversion efficiency, but also the maximum allowable load current for the transistor driver with small layout size, when compared to the buck converter with the earlier scheme. The measurements show that when the supply voltage is 2.5 V and the load current is 150 mA, the efficiency of the buck converter with the earlier scheme is 82%, whereas the efficiency of the buck converter with the proposed scheme is 92%, showing a maximum improvement of 10%. The designed buck converter uses the 0.35- μm-thick gate oxide CMOS process, and at 2.5-5 V of voltage, can supply up to 380 mA of load current. The total chip size is 2.7 mm2.

High-performance error amplifier for fast transient DC-DC converters

Implementation of on-chip passive elements and efficient regulation schemes are key aspects of fully integrated dc-dc converter design. This paper presents a 50-MHz fully integrated buck converter equipped with packaging inductors. These inductors include parasitic inductances of the bonding wires and lead frames in the package. They have significantly better Q factors than the best on-chip inductors implemented on silicon. This paper also presents full-swing and low-swing gate drivers for efficient regulation of high-frequency switching converters. The low-swing driver uses the drop voltage of a diode-connected transistor and is applied in a fabricated converter to reduce the gate driving loss caused by the high switching operation. The proposed converter is designed and fabricated using a 0.13-μm 1-poly 6-metal CMOS process. The fully integrated buck converter achieves 68.7% and 76.8 % efficiency for 3.3 V/2.0 V and 2.5 V/1.8 V conversions, respectively, while providing a load current of 250 mA.

5-V Buck Converter Using 3.3-V Standard CMOS Process With Adaptive Power Transistor Driver Increasing Efficiency and Maximum Load Capacity

A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-μ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma (ΔΣ) modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-Ω load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-Ω load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7-4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm2 and achieves a THD+N of 0.018%.

A 50-MHz Fully Integrated Low-Swing Buck Converter Using Packaging Inductors

We present the design of a single-chip delta-sigma (DeltaSigma) modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates output pulse signals using a single-bit fourth-order high-performance DeltaSigma modulator. To achieve a high signal-to-noise ratio and ensure system stability for a large input range, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard 0.18-mum CMOS process. The active area of the chip is 1.6 mm2. It operates for the signal bandwidth from 20 Hz to 20 kHz. The measured total harmonic distortion plus noise at the 32-Omega load terminal is 0.022% from a single 3-V power supply.

A 0.018% THD+N, 88-dB PSRR PWM Class-D Amplifier for Direct Battery Hookup

A 0.6-V 34-muW delta-sigma modulator implemented by using a standard 0.13-mum complementary metal-oxide-semiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order delta-sigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 muW for the modulator, and the core chip size is 0.33 mm2 .

Class-D Audio Amplifier Using 1-Bit Fourth-Order Delta-Sigma Modulation

A low-cost and comprehensive built-in self-test (BIST) methodology for analog and mixed-signal circuits is described. We implement a time-division multiplexing (TDM) comparator to analyze the response of a circuit under test with minimum hardware overhead. The TDM comparator scheme is an effective signature analyzer for on-chip analog response compaction and pass/fail decision. We apply this scheme to an oscillation-test environment and implement a low-cost and comprehensive vectorless BIST methodology for high fault and yield coverage. Our scheme allows a tolerance in the output response, a feature necessary for analog circuits. Both oscillation frequency and oscillation amplitude are measured indirectly to increase the fault coverage. We provide a theoretical analysis of the oscillation that explains why the amplitude measurement is essential. Simulation results demonstrate that the proposed scheme can significantly reduce test time of the oscillation-test while achieving higher fault coverage.

A 0.6-V Delta–Sigma Modulator With Subthreshold-Leakage Suppression Switches

A new technique is proposed to analyze and compress the output responses from analog circuits. We first describe the subband filtering scheme to decompose responses from the analog circuit under test (CUT). A subband or wavelet filter takes the response, then generates the decomposed signals for each frequency band. The decomposed signal for each frequency band is rectified and then fed into its respective integrator. Two kinds of wavelet filters are used to decompose the test response and effectively detect the faults in the circuit. Implementation issues including hardware overhead are also discussed.

A comprehensive signature analysis scheme for oscillation-test

Mobile devices need to minimize their power consumption in order to maximize battery runtime, except during short extremely busy periods. This requirement makes dc-dc converters usually operate in standby mode or under light-load conditions. Therefore, implementation of an efficient regulation scheme under a light load is a key aspect of dc-dc converter design. This paper presents a multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control. The converter includes four phases operating in an interleaved manner in order to supply high current with low output ripple. The multiphase converter implements a rotating phase-shedding scheme to distribute the switching activity concentrated on a single phase, resulting in a distribution of the aging effects among the phases instead of a single phase. The proposed multiphase buck converter was fabricated using a 0.18 μm bipolar CMOS DMOS process. The supply voltage ranges from 2.7 V to 5 V, and the maximum allowable output current is 4.5 A.