Youngkil Choi

A 0.9-V 60-

A 0.9-V 60-muW delta-sigma modulator is designed using standard CMOS 0.13-mum technology. The modulator achieves 83-dB dynamic range in a signal bandwidth of 20 kHz with a sampling frequency of 2 MHz. The input-feedforward architecture is used to reduce the voltage swing of the integrators, which enables low-power amplifiers. By considering the characteristics of the modulator architecture, low-quiescent operational transconductance amplifiers are designed, which use positive feedback to increase dc gain. The designed modulator shows very high figure of merit among the state-of-the-art sub-l-V modulators.

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A multicenter exploratory study at three university hospitals was performed to evaluate the effect of oral cilostazol on intima media thickness (IMT) in diabetic patients. A total of 141 patients was recruited in this study and randomized into a cilostazol group and a placebo (control) group. One hundred and twenty patients completed the study (i.e. 60 on cilostazol and 60 on placebo). Biochemical profiles and the IMT of the common carotid artery (CCA) determined by high-resolution B-mode ultrasonography were measured at 0, 6, and 12 months after the oral administration of 100--200 mg of cilostazol or placebo (i.e. two or four times daily for 12 months). Clinical and biochemical characteristics, the treatment modality, and microvascular diabetic complications after randomization were not significantly different between the two groups after the study. In the cilostazol treatment group, left CCA average IMT significantly decreased from 0.94+/-0.03 to 0.91+/-0.02 mm at 6 months (P<0.05), and thereafter increased to 0.92+/-0.01 mm (P>0.05) at 12 months, whereas in the control group, it increased from 0.92+/-0.03 to 0.93+/-0.01 mm at 6 months (P>0.05), and to 0.94+/-0.01 mm at 12 months (P>0.05). As for the right CCA average IMT, it decreased from 0.83+/-0.03 to 0.82+/-0.01 mm at 6 months (P<0.05), and to 0.81+/-0.01 mm at 12 months (P<0.05) in the cilostazol group, whereas it increased from 0.87+/-0.03 to 0.89+/-0.01 mm at 6 months (P<0.05), and to 0.90+/-0.01 mm at 12 months (P<0.05) in the control group (P<0.05). After correction for risk factors such as blood pressure, smoking, and lipid profiles, there were significant changes in left and right CCA average IMT for both groups (P<0.05). Left and right CCA average IMT was significantly different between the two groups (P<0.05). After making statistical corrections for blood pressure, smoking, and lipid profiles, the differences between these two groups remained significant (P<0.05). Meanwhile, there were no differences between the groups in the change of risk factors such as BMI, blood pressure, blood sugar, HbA(1c), and lipid profiles. Generally, cilostazol was well tolerated and the most common side effect in the cilostazol group was headache (12/60), mostly early in the treatment regimen. The results suggest that oral cilostazol may be helpful in the treatment of atherosclerosis in type 2 diabetic patients, although conventional cardiovascular risk factors remained unmodified.

1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range

A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-μ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma (ΔΣ) modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-Ω load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-Ω load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7-4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm2 and achieves a THD+N of 0.018%.

Decrease in carotid intima media thickness after 1 year of cilostazol treatment in patients with type 2 diabetes mellitus

We present the design of a single-chip delta-sigma (DeltaSigma) modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates output pulse signals using a single-bit fourth-order high-performance DeltaSigma modulator. To achieve a high signal-to-noise ratio and ensure system stability for a large input range, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard 0.18-mum CMOS process. The active area of the chip is 1.6 mm2. It operates for the signal bandwidth from 20 Hz to 20 kHz. The measured total harmonic distortion plus noise at the 32-Omega load terminal is 0.022% from a single 3-V power supply.

A 0.018% THD+N, 88-dB PSRR PWM Class-D Amplifier for Direct Battery Hookup

A 0.6-V 34-muW delta-sigma modulator implemented by using a standard 0.13-mum complementary metal-oxide-semiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order delta-sigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 muW for the modulator, and the core chip size is 0.33 mm2 .

Class-D Audio Amplifier Using 1-Bit Fourth-Order Delta-Sigma Modulation

A fourth-order single-bit delta-sigma modulator is presented for sensor applications. The loop filter is composed of both feedback and feedforward paths, and the modulator is implemented using fully differential switched-capacitor techniques. A test chip was fabricated in a 0.18-mum standard complementary metal-oxide semiconductor (CMOS) process. The chip core area is 1.22 mm2, and its power consumption is 5.6 mW from a 3.0-V power supply. Measurement results show that a maximum 99-dB dynamic range is achievable at a clock rate of 3.2 MHz for the 20-kHz bandwidth. The designed chip is targeted for high-accuracy and wide-bandwidth sensor applications such as the resistor-based current sensors and the Hall-effect sensors in motor control systems.

A 0.6-V Delta–Sigma Modulator With Subthreshold-Leakage Suppression Switches

This paper presents a bufferless interface that can be directly connected to a single-ended capacitive sensor such as an electret condenser microphone. A high-input impedance interface is developed using only a continuous-time loop filter, whereas conventional interface circuits are composed of a buffer, a preamplifier, an antialiasing filter, and a high-order switched-capacitor loop filter. Equipped with an active gm-C integrator, this interface chip is designed to implement all the required functions, i.e., high-input impedance buffering, preamplification, antialiasing filtering, and analog-to-digital conversion. The inherent antialiasing filtering function also provides a significant advantage in terms of silicon areas and power consumption. The complete interface channel achieves a 75-dB dynamic range and a 60.3-dB signal-to-noise-plus-distortion ratio over a 25-kHz signal band, which satisfies the requirements for electret microphones. The power consumption of the interface channel is 600 μW, and the chip dissipates a total of 860 μW from the 3.3-V supply.

A 99-dB DR Fourth-Order Delta–Sigma Modulator for 20-kHz Bandwidth Sensor Applications

Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a fully synthesised digital decimation filter that provides a time-to-market advantage. The filter consists of a cascaded integrator-comb filter and two cascaded half-band FIR filters. A canonical signed-digit representation of the filter coefficients is used to minimise the area and to reduce the hardware complexity of the multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated by using 0.25-μm CMOS technology with an active area of 1.36 mm2 and shows 4.4 mW power consumption at a clock rate of 2.8224 MHz. Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time. This is possible because the filter does not have process-dependent ROM or RAM circuits.

A Bufferless Interface for Single-Ended ECM Sensors

This paper presents the design of a continuous-time delta-sigma (ΔΣ) modulator for acoustic sensor networks. A feed-forward structure without a summing block is used to reduce the power consumption of the ΔΣ modulator. A high-linearity active-RC filter is used to improve the resolution of the ΔΣ modulator. A low-power, high-resolution fourth-order continuous-time ΔΣ modulator with 1-bit quantization was developed by using 0.13-µm, 1-poly 8-metal CMOS technology, with a core area of 0.58 mm². Simulation results show that the modulator achieved 91.3-dB SNDR (signal-to-noise plus distortion ratio) over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating 290 µW of power from a 3.3-V supply.

Fully synthesised decimation filter for delta-sigma A/D converters

In this paper, we present a fourth-order single-bit delta-sigma modulator with wide dynamic range. This modulator is suitable for distributed sensor and audio codec applications. This chip was fabricated in a 0.18- mum one-poly, four-metal CMOS technology, and occupies 1.22-mm2 active area. The circuit is clocked at 3.2 MHz and the overall power consumption is 5.6 mW from a 3.0 V power supply. Experimental results show a maximum dynamic range of 99 dB within a 20- kHz bandwidth.