Hyunsoo Ha

12.6 A 160nW 63.9fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes

Recent advances in nW-level wireless sensor nodes have created opportunities in emerging applications such as bio-implantable telemetry, smart healthcare, and environmental monitoring [1]. At the same time, there are many circuit and system design challenges to achieving high functionality in such ultra-low-power microsystems. One of the key sensing modalities in these systems is capacitive sensing. With zero static current during signal readout, capacitive sensing is well suited to ultra-low-power microsystems and has been widely adopted in the sensing of pressure [2,3], displacement [4], and humidity [5].

A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate

The CDR circuit is a key enabling block in high-speed serial links. With an external reference clock for frequency acquisition, high-performance CDR circuits typically operate at a single pre-defined data rate. In rapidly growing telecommunication applications, however, it is desirable for a CDR circuit to be able to cover a wide range of bit rates for improved flexibility. In the WDM technique, for example, the data can be transmitted with different bit rates. Thus, it is desired that the CDR circuit detects the change in the input data rate and automatically acquire the new data rate without any need for external programming.

A 0.5-V, 1.47-

A 13-bit successive approximation analog-to-digital converter (ADC) is presented for an ultralow-power sensor interface. Capacitor error compensation is achieved by swapping the roles of two identical capacitor banks in a digital-to-analog converter. The ADC is implemented in a standard 0.13-μm CMOS. With a single supply voltage of 0.5 V and a rail-to-rail conversion range, the ADC dissipates 1.47 μW at a sampling rate of 40 kS/s. It shows a figure of merit of 17.9 fJ/conversion-step with an effective number of 11.0 bits.

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In high-speed communication with a data rate of multi-Gb/s, the crosstalk noise induced by electromagnetic coupling is becoming a significant noise source, requiring careful considerations in the design of transceiver circuits as well as physical dimension of the transmission lines. When an input voltage of V_i is applied to one of two parallel transmission lines, the induced voltages at the victim line by near-end crosstalk (NEXT) and far-end crosstalk (FEXT) can be expressed as V_NEXT(t)=1/4[C_m/C_S+L_m/L_S]·{Vi(t)-Vi(t-2t_f)}, V_NEXT(t)=t_f/2[C_m/C_S-L_m/L_S]·dVi(t-t_f)/dt (1) where t_f, C_m, C_S, L_m and L_S represent the time-of-flight, the mutual, self-capacitances, mutual, and self-inductances of the transmission line per unit length, respectively. Though NEXT has more energy due the inductive coupling added to the capacitive coupling, the wide distribution in time over 2t_f results in a small peak noise and is a concern only in high-speed low-voltage differential signaling. However, FEXT in parallel microstrip lines causes a significant peak noise due to smaller capacitive coupling by inhomogeneous structure with the upper side exposed to air. The effect of FEXT turns out to be non-zero signal delay at the receiver side, presenting a serious performance-limiting factor in single-ended high-density parallel links such as memory interface.

40-kS/s 13-bit SAR ADC With Capacitor Error Compensation

This paper presents a low-power resistive sensor interface circuit with correlated double sampling which reduces the effect of amplifier offset and enables time-interleaved single-to-differential sampling. The proposed sampling scheme, used with a 12b SAR-type analog-to-digital converter, effectively doubles the input signal and improves linearity. The fabricated chip in 0.13μm CMOS demonstrates a sampling rate of 1-kS/s and a dynamic range of 117dB with a maximum conversion error of 0.32-percent while consuming only 11.3-μW from single supply voltage of 0.5V.

A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation

Multiple energy-efficient CDCs are proposed for millimeter sensor nodes. Compared to the state-of-the-art, these CDCs achieves excellent energy efficiency, high SNR, and wide input range with a variety of techniques. These include correlated double sampling in front of a SAR ADC, incremental delta-sigma conversion with a zoom-in SAR converter, energy-efficient dual-slope conversion, and fully-digital iterative delay-chain discharge conversion.

A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling

Miniaturized biomedical sensors promise improved quality of medical diagnosis and treatment. However, the realization of such implantable devices faces challenges due to limited battery capacity and energy sources. This paper describes new circuit techniques for miniaturized biomedical sensors, with particular emphasis on bio-signals sensing front end, power management, and communication.

Energy-Efficient CDCs for Millimeter Sensor Nodes

A transistor-based background on-chip self-calibration technique is proposed to obtain PVT-independent circuit parameters. With little implementation complexity, the proposed direct I-V calibration of performance determining transistors efficiently achieves stable operation of precision circuits. As an example application to a design of a PLL, the calibration scheme adjusts critical parameters such as VCO gain and charge-pump current to achieve adaptive bandwidth characteristics. The PLL, implemented in a 0.18 mum CMOS, shows a wide lock-range of 10 MHz-1 GHz with the rms jitter of 5.7 ps at 1 GHz.

Circuit techniques for miniaturized biomedical sensors.

This book chapter will discuss advancements in analog circuit design specifically for various wearable healthcare applications. There are a number of general trends that can be observed in this field, like multimodal sensing applications, which will be discussed. There will be a focus on analog circuits for some of the most relevant signal modalities including ExG, bio-impedance, and photoplethysmogram (PPG). Common circuit topologies and some recent state-of-the-art implementations for those will be discussed.

A transistor-based background self-calibration for reducing PVT sensitivity with a design example of an adaptive bandwidth PLL

This paper presents a highly reconfigurable analog front-end (AFE) IC supporting multi-modal (bio)signal monitoring. By efficiently reusing core components, the reconfigurable AFE channel occupies an area of 1.1mm2 while supporting four acquisition modes, i.e. biopotential (ExG), bio-impedance (BioZ), galvanic skin response (GSR) and general purpose analog (GPA). State-of-the-art sensitivity has been achieved at low power by employing both chopping and dynamic element matching (DEM). The reconfigurable AFE channel consumes 36μW maximum from a 1.2 V supply.