Seon-Kyoo Lee

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface

This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 μm CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 μW at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 f J/conversion-step.

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18

The resolution of multi-bit linear TDC is closely related to process technology since the minimum resolvable time quantity is proportional to one-inverter delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3]. Since the time resolution is determined by the difference between two inverter delays, a large number of inverter stages is required to cover a large detection range, resulting in long conversion time and high power consumption. Well-established data-conversion architectures have also been sought to achieve both large detection range and high resolution [4,5]. The two-step TDC was proposed to improve both the resolution and detectable range by amplifying the time residue after the coarse conversion for the fine conversion [4]. But, the previous time amplification schemes [4, 6] use metastability and suffer from small input range and gain uncertainties due to nonlinearity and PVT variations. This paper presents a power-efficient and wide dynamic range sub-exponent TDC. Based on a cascaded chain of 2× time amplifiers, the TDC generates the exponent-only information for the fractional time difference.

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The CDR circuit is a key enabling block in high-speed serial links. With an external reference clock for frequency acquisition, high-performance CDR circuits typically operate at a single pre-defined data rate. In rapidly growing telecommunication applications, however, it is desirable for a CDR circuit to be able to cover a wide range of bit rates for improved flexibility. In the WDM technique, for example, the data can be transmitted with different bit rates. Thus, it is desired that the CDR circuit detects the change in the input data rate and automatically acquire the new data rate without any need for external programming.

m CMOS

An energy-efficient 3 Gb/s current-mode interface scheme is proposed for on-chip global interconnects and silicon interposer channels. The transceiver core consists of an open-drain transmitter with one-tap pre-emphasis and a current sense amplifier load as the receiver. The current sense amplifier load is formed by stacking a PMOS diode stage and a cross-coupled NMOS stage, providing an optimum current-mode receiver without any bias current. The proposed scheme is verified with two cases of transceivers implemented in 65 nm CMOS. A 10 mm point-to-point data-only channel shows an energy efficiency of 9.5 fJ/b/mm, and a 20 mm four-drop source-synchronous link achieves 29.4 fJ/b/mm including clock and data channels.

A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate

A new concept of floating-point-number representation is implemented in a time-to-digital converter (TDC), which adaptively scales its resolution according to the amount of input difference. With a fixed 6-bit significand number, the TDC provides five cases of the exponent (x1, x2, x4, x8, and x16) to indicate the scale information. A digital phase-locked loop (PLL) with the TDC is implemented in a 0.18-μm CMOS. The TDC shows the minimum resolution of 3 ps with a total conversion range of 3.5 ns, the maximum operating frequency of 80 MHz, and the power consumption of 18 mW at 75 MHz. The PLL shows a lock range of 0.9-1.25 GHz and a root-mean-square jitter of 3.5 ps at 1.2 GHz.

Current-Mode Transceiver for Silicon Interposer Channel

An all-digital DLL is designed to generate low jittery 40 phases in a continuous lock range of 110 MHz to 1.4 GHz. The DLL is driven by dual loops-one for phase lock and the other for offset calibration. The two loops are updated by a chopping PD which adaptively extracts valid information for each loop, one at a time. For the optimal 1-bit delay resolution in the entire lock range, a piecewise profiling of delay line is also proposed. The DLL, fabricated in a 0.13 CMOS, reveals the best linearity performance compared with previously reported works, showing a DNL of less than 0.3 LSB and a INL of less than 0.8 LSB in the entire lock range up to 1.4 GHz. With the piecewise-fitted delay line, the amount of peak-to-peak and rms jitters induced by DLL operation is controlled to be less than 0.825% and 0.2% of the clock period, respectively. Power consumption was 74.4 mW at the supply voltage of 1.2 V.

A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-

A low-power palm-size microwave power module for portable microwave-excited plasma applicable to biomedicine is integrated on a single printed circuit board for the first time. The designed board includes a power amplifier chip, a phase-locked loop (PLL) chip, and an impedance matching network with microstrip lines. In addition, as a part of the true one-chip integration of the plasma power module, the PLL is designed and fabricated in a semiconductor chip with a 0.18-μm CMOS technology for dedicated use to our plasma source. For the plasma generator, a 900-MHz coaxial transmission line resonator is used with argon gas flow. The designed plasma source is applied to the inactivation of S. mutans, showing three-log reduction within 180-s treatment. Measurements for the different initial concentrations (from 105 to 10 9 CFU/mL) are also conducted, and the outcomes are discussed. The results verify the feasibility of the proposed integrated microplasma source for use in dental treatments.

\mu\hbox{m}

This paper presents an adaptive far-end crosstalk cancellation scheme for a single-ended parallel receiver. The adaptation engine is embedded in a single representative channel CDR, and the receiver efficiently reduces the crosstalk noise with a minimal cost in hardware and power consumption. In addition, the proposed scheme can be applied to any given CDR and equalizing circuits. The receiver is fabricated in 0.13 μm CMOS technology and achieves a reduction of FEXT-induced jitter up to 75%. The receiver consumes 65 mW at 5 Gb/s (4.3 mW/Gb/s/pin) including a PLL for global clock distribution.

CMOS

NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and high-throughput performance. In recent years, a SATA interface supporting only up to 600MB/S throughput has hindered the accelerating performance growth of SSDs due to the host bandwidth limit. A PCI Express (PCIe) has emerged to close the limit because it can deliver 1GB/s throughput per lane and can be scaled to multi-lane to improve bandwidth. Accordingly, the SSD performance bottleneck has moved from the host interface to the NAND flash interface. In a memory system, a die-stacking technology in a NAND flash multi-chip package (MCP) effectively increases capacity and throughput performance in terms of PCB complexities and power consumption compared to a method increasing the number of channels. However, the multi-drop bus topology on NAND interfaces severely affects I/O speed degradations due to channel reflections and inter-symbol interference (ISI) resulting from large capacitive loadings. The undeniable paradox between larger storage capacity and higher I/O bandwidth has become a key challenge to reach enterprise-class SSDs. To overcome this issue, this paper presents a frequency-boosting interface chip (F-Chip) to boost I/O speeds while meeting capacity requirements. A 2Tb NAND flash MCP with 1GB/s toggle DDR interface is accomplished by incorporating the F-Chip into the NAND MCP including a 16-die stacked 128Gb NAND flash.

A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL

NAND flash memory is widely used as a cost-effective storage with high performance [1-2]. This paper presents a 128Gb multi-level cell (MLC) NAND flash memory with a 150 cells/string structure in 14nm CMOS that can be used as a cost-effective storage device. This paper also introduces several approaches to compensate for reliability and performance degradations caused by the 14nm transistors and the 150 cells/string structure. A technique was developed to suppress the background pattern dependency (BPD) by applying a low voltage to upper word lines (WLs) - the drain side(SSL side) WLs with respect to the location of the selected WL - during the verify sequence. Two techniques are also used to improve the program performance: equilibrium pulse scheme and smart start bias control scheme (SBC) in the MSB page. In addition, the first cycle recovery (FCR) of read enable (RE) and the bi-directional data strobe (DQS) is used to achieve a high speed I/O rate. As a result, a 640μs program time and a 800MB/s I/O rate is achieved.