Hong-June Park

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface

This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 μm CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 μW at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 f J/conversion-step.

Empirical equations on electrical parameters of coupled microstrip lines for crosstalk estimation in printed circuit board

Empirical equations for the self and mutual capacitance and inductance (C/sub s/, C/sub m/, L/sub s/, L/sub m/) of coupled microstrip lines in a printed circuit board were derived from the numerical simulation results to reduce the computation time for crosstalk estimation. Comparison of the measured C/sub s/, C/sub m/, L/sub s/ and L/sub m/ values with the derived empirical equations showed good agreements. Also in the near-end and far-end crosstalks, good agreements were obtained between measurements and the derived empirical equations. Microstrip lines embedded in the homogeneous dielectric material as well as those in the inhomogeneous medium with one side exposed to air were considered in this work. Based on the derived empirical equations, a design guide on the spacing between microstrip lines was established.

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18

The resolution of multi-bit linear TDC is closely related to process technology since the minimum resolvable time quantity is proportional to one-inverter delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3]. Since the time resolution is determined by the difference between two inverter delays, a large number of inverter stages is required to cover a large detection range, resulting in long conversion time and high power consumption. Well-established data-conversion architectures have also been sought to achieve both large detection range and high resolution [4,5]. The two-step TDC was proposed to improve both the resolution and detectable range by amplifying the time residue after the coarse conversion for the fine conversion [4]. But, the previous time amplification schemes [4, 6] use metastability and suffer from small input range and gain uncertainties due to nonlinearity and PVT variations. This paper presents a power-efficient and wide dynamic range sub-exponent TDC. Based on a cascaded chain of 2× time amplifiers, the TDC generates the exponent-only information for the fractional time difference.

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A serpentine guard trace is proposed to reduce the peak far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines on printed circuit boards. The vertical sections of the serpentine guard increase the mutual capacitance without much changing the mutual inductance between the aggressor and victim lines. This reduces the difference between the capacitive and inductive couplings and hence the far-end crosstalk. Comparison with the no guard, the conventional guard, and the via-stitch guard shows that the serpentine guard gives the smallest values in both the peak far-end crosstalk voltage and the timing jitter. The time domain reflectometer (TDR) measurement shows that the peak far-end crosstalk voltage of serpentine guard is reduced to 44% of that of no guard. The eye diagram measurement of pseudo random binary sequence (PRBS) data shows that the timing jitter is also reduced to 40% of that of no guard.

m CMOS

This paper describes the first implementation of the well-known cyclic ADC architecture into a time-to-digital converter. With an asynchronous clocking scheme, an all-digital 1.5b time-domain multiplying DAC (MDAC) is repetitively used for 8b conversion. The MDAC is based on a 2 × time amplifier with an offset-compensated gain calibration scheme. The proposed cyclic TDC, fabricated in a 0.13 μm CMOS, shows a resolution of 1.25 ps with a total conversion range of ±160 ps, the maximum operating frequency of 100 MHz, and a power consumption of 4.3 mW at 50 MHz. The measured DNL and INL are ± 0.7 LSB and - 3 to + 1 LSB, respectively.

A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines

A digital-domain calibration method is proposed for a split-capacitor DAC (split-CDAC) used in a differential-type 11-bit SAR ADC. It calibrates the nonlinearities of SAR ADC due to the DAC capacitance mismatch as well as the two parasitic capacitances connected in parallel with each of the bridge capacitor and the LSB bank of split-CDAC. The proposed ADC does not require any additional analog circuits for calibration, because it utilizes one of the two split-CDACs to measure the error codes of the other split-CDAC. During the normal A/D conversion step, the 11.5-bit raw SAR code output of ADC is added to the pre-measured error codes to generate the 11-bit calibrated output code. The analog block of the ADC was fabricated in a 0.13- μm CMOS process, and the digital block was implemented in a FPGA. The measured SNDR and SFDR are 61.6 dB (ENOB 9.93 bits) and 78 dB at the Nyquist rate with a 5 kHz sine wave input. INL and DNL are measured to be +0.96/-0.98 LSB, and +0.96/-0.97 LSB, respectively. This work extends the prior work by utilizing an additional 0.5-bit raw SAR code to eliminate the missing code, and by employing a temporal averaging with a FIR LPF to measure the error code reliably in spite of the supply noise.

A 1.25 ps Resolution 8b Cyclic TDC in 0.13

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of the second one is an even multiple. An interpolation operation is performed at the second coarse delay chain, which reduces both the resolution of the coarse delay block and the delay range of the fine block to half. This increases the maximum output frequency of the DCO while it maintains the wide frequency range. The ADPLL with the proposed DCO was fabricated in a 0.18 mum CMOS process with the active area of 0.32 mm2 . The measured output frequency of the ADPLL ranges from 33 to 1040 MHz at the supply of 1.8 V. The measured rms and peak-to-peak jitters are 13.8 ps and 86.7 ps, respectively, at the output frequency of 950 MHz. The power consumption is 15.7 mW.

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The CDR circuit is a key enabling block in high-speed serial links. With an external reference clock for frequency acquisition, high-performance CDR circuits typically operate at a single pre-defined data rate. In rapidly growing telecommunication applications, however, it is desirable for a CDR circuit to be able to cover a wide range of bit rates for improved flexibility. In the WDM technique, for example, the data can be transmitted with different bit rates. Thus, it is desired that the CDR circuit detects the change in the input data rate and automatically acquire the new data rate without any need for external programming.

m CMOS

A CMOS LADFE (look-ahead decision feedback equalization) receiver with a pin-to-pin time skew compensation was proposed and implemented for high-speed chip-to-chip communication such as multi-drop DRAM interface. The look-ahead scheme in DFE input buffer increased the maximum data rate from 1.4 Gbps to 2.2 Gbps. Different sampling clock was synthesized for each pin by using an /spl times/2 over-sampling scheme. Active chip area per pin is 100 /spl mu/m/spl times/800 /spl mu/m with a 2.5 V, 0.25 /spl mu/m CMOS process.

A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits

Ultrasound imaging is widely used for medical diagnosis, because it is harmless to the human body and has real-time processing capability. Usually the focusing (beamforming) operation is performed for both TX and RX. The RX focusing is performed by an RX beamformer [1-5], which consists of delay elements and adders. Nowadays, digital beamformers (DBF) are mostly used for conventional ultrasound imaging because of high SNR. Recently, 2D ultrasound transducers have been introduced for 3D imaging. Since the 2D transducer has a huge number of transducer elements (e.g., 9216 for a 72×128 array), it cannot use DBF because of the huge number of required ADCs and wires inside the probe cable. Therefore, analog beamforming must be performed, at least at the front stage of the 2D transducer.In this work, where a 2D CMUT array is used, the maximum delay difference among transducer elements is 8μs with a maximum steering angle of 45° and a maximum focal depth of 15cm. The target sampling resolution is 6.25ns (λc / 53.3) with a carrier frequency of 3MHz. An analog-digital-hybrid architecture and a non-uniform sampling scheme are used for the RX beamformer of this work to achieve the wide dynamic range of delay time and small chip-area. The RX beamformer consists of 8 analog beamformers (ABF) followed by a single DBF, as shown in Fig. 24.8.1. An ABF performs the focusing operation for the input signals of the adjacent 8 channels to generate an analog output signal. The 8 analog output signals from the 8 ABFs are applied to the DBF. The DBF converts the 8 analog input signals into the 8 digital signals, and then performs the focusing operation on the 8 digital signals to generate a digital output signal for every focal point.