I. Aberg

Strained silicon MOSFET technology

Mobility and current drive improvements associated with biaxial tensile stress in Si n- and p-MOSFETs are briefly reviewed. Electron mobility enhancements at high channel doping (up to 6 /spl times/ 10/sup 18/ cm/sup -3/) are characterized in strained Si n-MOSFETs. For low inversion layer carrier concentrations, channel-dopant ionized impurity scattering does reduce the strain-induced mobility enhancement, but the enhancement is recovered at higher inversion charge concentrations, where screening is efficient. Mobility enhancement in strained Si p-MOSFETs is also discussed. There are process integration challenges and opportunities associated with this technology. Dopant diffusion, and its impact on profile engineering in strained Si CMOS structures, is one example. While the slower diffusion of B in Si/sub 1-x/Ge/sub x/ enables improved doping profile control, the diffusivity of the n-type dopants is dramatically enhanced in Si/sub 0.8/Ge/sub 0.2/.

Continuous MOSFET performance increase with device scaling: the role of strain and channel material innovations

A simple model that links MOSFET performance, in the form of intrinsic switch delay, to effective carrier velocity in the channel is developed and fitted to historical data. It is shown that nearly continuous carrier velocity increase, most recently via the introduction of process-induced strain, has been responsible for the device performance increase commensurately with dimensional scaling. The paper further examines channel material innovations that will be required in order to maintain continued commensurate scaling beyond what can be achieved with process-induced strain, and discusses some of the technological tradeoffs that will have to be faced for their introduction.

Strain relaxation in patterned strained silicon directly on insulator structures

Strain relaxation is studied in strained silicon directly on insulator (SSDOI) substrates patterned with nanoscale features. Using interference lithography, biaxially strained SSDOI substrates with 30nm thick strained Si on insulator films were patterned into grating structures with 90nm wide stripes, and arrays of 80nm×170nm pillars. The strain profiles of these patterned structures were examined by ultraviolet Raman spectroscopy. Raman analysis of the SSDOI gratings indicates strain relaxation in the 90nm wide stripes, compared to the strain measured in unpatterned portions of the SSDOI wafer. Three-dimensional finite-element modeling of the stress distributions in the grading structures predicts that 95% of the strain is maintained in the direction along the length of the stripes. These simulations are used to decouple the strain components along the width and length of the SSDOI grating structure, inferred from Raman measurements. The results are consistent with substantial stress relaxation across th...

Electron Transport in Strained-Silicon Directly on Insulator Ultrathin-Body n-MOSFETs With Body Thickness Ranging From 2 to 25 nm

The electron effective mobility in ultrathin-body n-channel metal-oxide-semiconductor field-effect transistors fabricated on Ge-free 30% strained-Si directly on insulator (SSDOI) is mapped as the body thickness is scaled. Effective mobility and device body thickness were extracted using current-voltage and gate-to-channel capacitance-voltage measurements as well as cross-sectional transmission electron microscopy. Devices with body thicknesses ranging from 2 to 25 nm are studied. Significant mobility enhancements ( ~1.8x) compared to unstrained SOI are observed for 30% SSDOI with body thicknesses of above 3.5 nm. The mobility exhibits a sharp drop as the body thickness is scaled below 3.5 nm

Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs

The combination of channel mobility-enhancement techniques such as strain engineering with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future technology nodes. The tradeoff between transport enhancement and OFF-state leakage current is compared experimentally for UTB MOSFETs in two types of materials: 1) strained Si directly on insulator (SSDOI) and 2) strained Si/strained Si/sub 1-z/Ge/sub z/ (z=0.46-0.55)/strained Si heterostructure-on-insulator (HOI). SSDOI of moderate strain level (e.g. /spl sim/ 0.8%) yields high electron-mobility enhancements for all electron densities, while high strain levels (e.g. /spl sim/ 1.6%) are required to obtain hole-mobility enhancements at high inversion charge densities. HOI is demonstrated to have similar electron-mobility characteristics to SSDOI, while hole mobilities are improved and can be maintained at high inversion charge densities. Hole mobility in strained channels with thickness below 10 nm is studied and compared for SSDOI and HOI. As the channel thickness is reduced, mobility decreases, as in unstrained silicon-on-insulator (SOI), though hole-mobility enhancements are demonstrated into the ultrathin-channel regime. Increased OFF-state leakage currents are observed in HOI compared to SSDOI and SOI. For a 4-nm-thick buried SiGe layer, leakage is reduced relative to devices with thicker SiGe channels.

Electron and hole mobility enhancements in sub-10 nm-thick strained silicon directly on insulator fabricated by a bond and etch-back technique

Electron and hole mobility enhancements are studied in Ge-free strained silicon directly on insulator fabricated by a bond and etch-back technique, for the first time. For inversion charge densities of 10/sup 13/ cm/sup -2/, electron and hole mobility enhancements of 100% (n-MOSFET, 30% effective Ge content, 15 nm-thick) and 50% (p-MOSFET, 40% effective Ge, 6 nm-thick), respectively are measured in fully depleted strained Si. For a biaxial strain level of 1.25% (30% effective Ge), hole mobility is the same for body thicknesses of 25 and 13 nm, and drops by no more than 5% for a body thickness of 8.5 nm. There is no evidence of strain relaxation, despite a generous thermal budget.

High electron and hole mobility enhancements in thin-body strained Si/strained SiGe/strained Si heterostructures on insulator

Fully depleted MOSFETs were fabricated on strained Si/strained SiGe (46% Ge)/strained Si heterostructures on insulator (HOI) for the first time, demonstrating both high electron and hole mobility enhancements while maintaining excellent subthreshold characteristics. The total thickness of the heterostructure on insulator is less than 25 nm. At an inversion charge density of 1.5/spl times/10/sup 13/ cm/sup -2/, mobility enhancements of 90% and 107% are obtained for electrons and holes respectively. The mobility increases as the cap thickness is reduced to 2 nm. HOI offers superior hole mobility than 40% strained silicon directly on insulator at all vertical fields, when the cap thickness is below 5 nm.

Hole transport in UTB MOSFETs in strained-Si directly on insulator with strained-Si thickness less than 5 nm

Hole transport is studied in ultrathin body (UTB) MOSFETs in strained-Si directly on insulator (SSDOI) with a Si thickness down to 1.4 nm. In these Ge-free SSDOI substrates, the Si is strained in biaxial tension with strain levels equivalent to strained-Si on relaxed SiGe, with Ge contents of 30 and 40% Ge. The hole mobility in SSDOI decreases slowly for Si thicknesses above 4 nm, but drops rapidly below that thickness. Relative to silicon-on-insulator control devices of equal thickness, SSDOI displays significant hole mobility enhancement for Si film thicknesses above 3.5 nm. Peak hole mobility is improved by 25% for 40% SSDOI relative to 30% SSDOI fabricated by the same method, demonstrating the benefits of strain engineering for 3.1-nm-thick UTB MOSFETs.

Fabrication of strained Si/strained SiGe/strained Si heterostructures on insulator by a bond and etch-back technique

This paper discusses the fabrication of strained Si/strained SiGe/strained Si heterostructures on insulator by a bond and etch-back technique with total thickness of 25 nm. We have shown that the etch back process does not roughen the surface. By secondary ion mass spectroscopy (SIMS), we have shown a reduction in peak Ge fraction from the as grown 55% to 50% as a result of thermal processing.

Transport and leakage in super-critical thickness strained silicon directly on insulator MOSFETs with strained Si thickness up to 135 nm

In this work, we study both FD- and PD-SSOI with aggressive T/sub Si/ of up to 135 nm for 14% SSOI (14% Ge equivalent strain). We have demonstrated that mobility in 14% SSOI is independent of the strained Si thickness, even for as grown films 10/spl times/ thicker than the critical thickness. Off-state current also remains independent of T/sub Si/. The successful fabrication of PD-SSOI with electron mobility enhancement maintained at 1.5/spl times/, for high channel doping and strained Si thickness up to 135 nm, was also demonstrated, showing promise for thicker film PD-SOI applications.