I-Jen Chao

Integrated potentiostat for electrochemical sensing of urinary 3-hydroxyanthranilic acid with molecularly imprinted poly(ethylene-co-vinyl alcohol)

Changing demographics, the rise of personalized medicine and increased identification of biomarkers for diagnosis and management of chronic disease have increased the demand for portable bioanalytical instrumentation and point-of-care. The recent development of molecularly imprinted polymers enables production of low cost and highly stable sensing chips; however, the commercially available and full functional instruments employed for electrochemical analysis have shortcomings in actual homecare applications. In this work, integrated circuits (ICs) for monolithic implementation of voltammeter potentiostat with a large dynamic current range (5 nA to 1.2 mA) and short conversion time (10 ms) were fabricated in a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The new instrumentation was tested with molecular imprinted sensors for 3-hydroxyanthranilic acid (3HAA) in urine. The sensor consisted of molecular imprinted of poly(ethylene-co-vinyl alcohol)s (abbreviated as EVALs) for implementation in a flow injection analysis system. The EVAL containing 32 ethylene mol% had the highest imprinting effectiveness for the target molecules. Fit-for-purpose figures of merit were achieved with a limit-of-detection (LOD) of 3.06 pg/mL. The measurements obtained in real undiluted urine samples fell within the reference concentration range of 50-550 ng/mL.

A 12-bit 4-kHz incremental ADC with loading-free extended counting technique

In this design, a low-power incremental ADC employing the loading-free architecture for the extended counting technique is proposed. The proposed topology uses a multi-bit SAR ADC to complete the extended counting conversion, but the integrator of the preceding incremental ADC is not loaded by the DAC array of the SAR ADC, which means the opamp power can be reduced. This work adopts an incremental ADC to convert the first 5-bit MSB and a synchronous SAR ADC to convert the last 7-bit LSB, and thus totally 12-bit resolution can be obtained without calibration. The proposed topology is capable of achieving high resolution, and furthermore holds the power efficient advantage of SAR ADCs. The proposed ADC is implemented in a 0.18-μm 1P6M CMOS process. Under 4-kHz input signal bandwidth and 23.07-μW power consumption, the peak signal-to-noise and distortion ratio is 69.38 dB. The active core area including clock generator occupies of 0.33 mm2.

A 9-bit 50 MS/s CBSC pipelined ADC using time-shifted correlated double sampling

Comparator-based switched-capacitor (CBSC) circuit provides a solution for insufficient impedance of the transistor in the advanced process, but the accuracy suffers from the overshoot error caused by comparator delay. In this paper, a time-shifted correlated double sampling (TSCDS) scheme for CBSC circuit is proposed to alleviate the overshoot error as well as mitigating double loading. Moreover, we propose an overshoot correction technique to further suppress the overshoot after employing TSCDS. Speed bottleneck in the conventional CBSC circuit is limited by the fine discharging phase. With the proposed TSCDS and the overshoot correction, the CBSC circuit exploits the coarse charging and removes the fine discharging phase to achieve a 9-bit 50 MS/s pipelined ADC. Simulation results demonstrate a 54.3-dB SNDR is achieved with 3.65-mW power consumption in 90-nm CMOS process and 1.2-V supply.

A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique

This paper proposes a 3rd-order low-distortion delta-sigma modulator (DSM) structure, which uses the timing-sharing technique between the 2nd and 3rd integrators during one clock phase. Further, since the operation phase of the 1st integrator is different to those of the 2nd and 3rd integrators, the three integrators are realized in just single opamp by the opamp sharing. Therefore, the power consumption can be reduced greatly. Besides, the proposed DSM structure poses the feature of relaxed feedback timing. The quantization and DEM operation can be extended from a non-overlapping interval for a conventional low-distortion structure to half of the clock period. The proposed 3rd-order 4-bit DSM is implemented in a 90-nm CMOS process. Post-layout simulation shows that the modulator achieves 75.1-dB SNDR with 2.5-MHz input signal bandwidth and 80-MHz sampling frequency. The power consumption is only 1.42 mW with 61.1-fJ/conversion-step FOM, and the core area is 683 × 592 μm2.

An Inductively Powered Converter for Implantable Biochemical Sensor Signal Processing System

In this paper, we propose an inductively powered converter to convert the incoming RF energy into a DC voltage (3.3 V) which powers up the biochemical sensor signal processing system. The converter, which is constructed by clamper, voltage limiter, rectifier, and LDO regulator, is capable of delivering more than 330 muW from a receiver coil to the implant circuitry. The chip area is 0.12times0.48 mm 2 in the 0.35 mum CMOS process. The performance of the integrated converter has been tested, by using carrier signal in 13.56 MHz. The proposed converter has the merit of low cost, due to its use of the standard CMOS process, without the necessary of adding an extra ESD process.

Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing

This paper proposes a splittable amplifier technique that can be either decomposed into two identical halves or merged for enhancing the utilization of the amplifier power and alleviating the memory effect, when applying operational amplifier (opamp) sharing. In a two-phase clock system, the amplifier can be split into two identical small amplifiers in one phase simultaneously for use in two circuits. Next, the two small amplifiers can be merged into one amplifier in the other phase for usage in another circuit. Compared with the conventional opamp sharing, a more power-efficient amplifier arrangement is achieved in the split mode. In this paper, three individual sample-and-hold (S/H) circuits with the proposed technique are designed to demonstrate the efficiency of memory effect cancellation. The simulations show that in contrast to the output spectrum of two S/H circuits with conventional opamp sharing, the spurious tones due to the memory effect can be suppressed by at least 14.66 dB in the split mode and at least 7.32 dB in the combination mode with a 0.6-

A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer

\text{V}_{\text {P-P}}

Behavior model for comparator-based switched-capacitor SDM with relaxed DEM timing

input signal when using the proposed technique.

A Low-Cost Output Response Analyzer Circuit for ADC BIST

This paper presents a comparator-based OTA first-order discrete-time low-distortion sigma-delta modulator. A split data weighted averaging (DWA) algorithm logic is proposed to release the heavy burden of digital circuit while a 6 bit DAC is implemented in this work. In addition, a comparator-based OTA is used to reduce the power consumption. On the top of that, to achieve lower power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. The modulator core occupies an active area of 0.0275 mm2 in TSMC 90-nm 1P9M CMOS process. Experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.

A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder

This paper proposes a behavior model for comparator-based switched-capacitor (CBSC) circuits by using SIMULINK platform. In this model, the maximum available time is compared with the charge transfer time required in the CBSC circuit to identify whether the currents chosen are suitable or not. The model is efficient to determine the values of the coarse charging current and the fine charging current required for CBSC circuits in a sigma-delta modulator (SDM). To verify the behavior model, a 3rd order SDM which still retains a half of the clock cycle for quantization and dynamic element matching (DEM) is proposed and simulated. The simulation result shows that the value of SNDR achieves 82.23 dB when the sampling rate is 100 MS/s (OSR=16).