Hsin-Wen Ting

Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction

A transition-code based method is proposed to reduce the linearity testing time of pipelined analog-to-digital converters (ADCs). By employing specific architecture-dependent rules, only a few specific transition codes need to be measured to accomplish the accurate linearity test of a pipelined ADC. In addition, a simple digital Design-for-Test (DfT) circuit is proposed to help correctly detect transition codes corresponding to each pipelined stage. With the help of the DfT circuit, the proposed method can be applied for pipelined ADCs with digital error correction (DEC). Experimental results of a practical chip show that the proposed method can achieve high test accuracy for a 12-bit 1.5-bit/stage pipelined ADC with different nonlinearities by measuring only 9.3% of the total measured samples of the conventional histogram based method.

A Design of Linearity Built-in Self-Test for Current-Steering DAC

In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.

Histogram Based Testing Strategy for ADC

An improved histogram testing method for analog-to-digital converters (ADCs) is proposed. The proposed method reveals not only the static performance but also the dynamic ones, such as the effective number of bits (ENOB) with a sinusoidal input signal. Therefore, single histogram testing is performed rather than using both the histogram and spectral methods to reduce the total test cost. The proposed testing method was experimentally validated on a commercial 8-bit ADC to demonstrate it effectiveness. The experimental result indicated that the proposed histogram-based test method exhibits a good agreement to the measured results of the classical FFT-based method

Reconstructive Oscillator Based Sinusoidal Signal Generator for ADC BIST

This paper presents a reconstructive oscillator based sinusoidal signal generator which can produce both high and low frequency signals by switching the oscillator into different mode. In addition, analog and digital signals can be produced concurrently in both modes. Also, signal amplitude and oscillation frequency can be precisely controlled compared with pure analog signal generator. Except for a 1-bit D/A converter and analog filter, the circuits are entirely constructed by digital circuits. One can trade the digital hardware complexity to moderate the difficulties in designing the analog reconstructive filter. The generated high and low frequency signals are suitable to serve as the test stimuli in built-in self test methodology for A/D converters to extract the transmission and static parameters, respectively

A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design

In this paper, we propose a novel content addressable memory/winner take all-based longest prefix matching (CW-LPM) circuit for the network router application. This CW-LPM circuit not only provides a simple hardware-based solution without some traditional drawbacks such as reordering or unavoidable complex extra hardware, but also has features of low power, low cost, high search speed and scalability. We implemented this CW-LPM circuit by using the TSMC 0.18 mum 1P6M CMOS process with 128 words by 32 bits data configuration. The simulation results show that the proposed CW-LPM circuit works up to 250 MSearches/sec at 1.8-V supply voltage with power consumption of 6.89mW and 140 MSearches/sec at 1.25-V supply voltage. Consequently, the proposed CW-LPM circuit design meets the speed requirement of OC (optical carrier) -3072/160 Gb/s line rate multi-gigabit/sec Ethernet network

A time domain built-in self-test methodology for SNDR and ENOB tests of analog-to-digital converters

In this paper, a built-in self-test (BIST) methodology used to test the important transmission parameters, signal-to-noise-and-distortion (SNDR) and effective number of bits (ENOB), of analog-to-digital converters (ADCs) is proposed. A sigma-delta modulation based signal generator is presented which can concurrently produce high frequency analog sinusoidal test stimuli and digital sinusoidal reference signals on chip. Unlike conventional test methods which compute these parameters based on the spectrum information after fast Fourier transformation (FFT), the presented BIST scheme can directly determine the noise-and-distortion power density and SNDR in time domain. It can reduce the high cost of implementing FFT and windowing functional blocks, and alleviate the difficulty in setting the test frequencies and measurement conditions.

An on-chip concurrent high frequency analog and digital sinusoidal generator

A sigma-delta (/spl Sigma//spl Delta/) modulation based sinusoidal signal generator is exploited which can produce high frequency analog and digital signals concurrently. Except for a 1-bit DAC and band-pass filter, the circuits are entirely digital circuits. Using digital circuits, it is easier to integrate the function in silicon and verify itself. Also, signal amplitude and oscillation frequency can be precisely controlled compared with pure analog signal generator. The area of the proposed high frequency sinusoidal signal generator is low and thus it is suitable to be a built-in signal generator for mixed-signal ICs testing.

Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers

This study presents a 6-bit 2.7 GS/s low-power digital-to-analogue converter (DAC) for ultra-wideband transceivers. A ‘2(thermometer)+4(binary)’ segmented architecture is chosen to reach a compromise between the current source cells area and the operating speed of the thermometer decoder. In addition, the proposed pseudo-thermometer structure improves the DACs dynamic performance. The bipolar current source cell and latch clock delay technique are employed to reduce the power consumption in the analogue and digital parts, respectively. Moreover, the compact de-glitch latch presented in this study simplifies the conventional latch design and layout. This DAC was implemented in a standard 0.13 µm 1P8M complementary metal-oxide semiconductor technology with the active area of 0.0585 mm2. The measured differential non-linearity and integral non-linearity are less than 0.09 and 0.11 least significant bit, respectively. The measured spurious-free dynamic range is more than 36 dB over the Nyquist frequency at the sampling frequency of 2.7 GHz. The DAC consumes 5.4 mW with a near-Nyquist sinusoidal output at 2.7 GS/s, resulting in a better figure of merit of 31 fJ/conversion-step than other published arts.

Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST

In order to perform an on-chip test for characterizing both static and transmission parameters of embedded analog-to-digital converters (ADCs), this paper presents an oscillator-based reconfigurable sinusoidal signal generator which can produce both high and low frequency sinusoidal signals by switching the oscillator into different modes. Analog and digital signals can additionally be produced concurrently in both modes to provide not only test stimuli, but also reference responses for the ADC built-in self-test. The generated oscillation signal amplitude and frequency can be easily and precisely controlled by simply setting the oscillator clock frequency and initial condition coefficients. Except for a 1-bit digital-to-analog converter and smoothing filter, this proposed generator is constructed entirely by digital circuits, and hence easily integrates this silicon function and verifies itself before testing the ADCs.

Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing

This paper proposes a splittable amplifier technique that can be either decomposed into two identical halves or merged for enhancing the utilization of the amplifier power and alleviating the memory effect, when applying operational amplifier (opamp) sharing. In a two-phase clock system, the amplifier can be split into two identical small amplifiers in one phase simultaneously for use in two circuits. Next, the two small amplifiers can be merged into one amplifier in the other phase for usage in another circuit. Compared with the conventional opamp sharing, a more power-efficient amplifier arrangement is achieved in the split mode. In this paper, three individual sample-and-hold (S/H) circuits with the proposed technique are designed to demonstrate the efficiency of memory effect cancellation. The simulations show that in contrast to the output spectrum of two S/H circuits with conventional opamp sharing, the spurious tones due to the memory effect can be suppressed by at least 14.66 dB in the split mode and at least 7.32 dB in the combination mode with a 0.6-