I-Shan Michael Sun

Lateral high-speed bipolar transistors on SOI for RF SoC applications

This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental f/sub T//f/sub max/ of the high-speed device are 17/28 GHz, the second fastest reported f/sub T/ for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured f/sub T//f/sub max/ of 12/30 GHz and BV/sub CEO/ of over 25 V produces a Johnsons product well above 300 GHz /spl middot/V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.

Design of a rugged 60 V VDMOS transistor

Vertical double diffused MOSFET (VDMOS) is an established technology for high-current power-switching applications such as automotive circuits. The most serious failure mode is destructive damage during inductive switching, resulting from avalanche breakdown of the forward-blocking junction in the presence of high current flow. Improving the ruggedness of the device is achieved by enhancing its ability to absorb inductive energy under avalanche conditions. The purpose of the paper is to explore the possibility of improving the ruggedness of VDMOS through TCAD simulations. A p + -strip buried underneath an n + -source is proposed to suppress the turn-on of the parasitic bipolar transistor. VDMOS transistors with this design modification are expected to have higher ruggedness while maintaining its superior figure-of-merit.

Superjunction LDMOS with drift region charge-balanced by distributed hexagon p-islands

A new device structure suitable for practical implementation of silicon superjunction LDMOS is proposed. With hexagonal p-islands distributed in the drift region of a conventional LDMOS (SJ-HexLDMOS), the tradeoff between breakdown voltage (BV/sub dss/) and specific on resistance (R/sub on,sp/) can be improved. Maximum efficiency in depleting the drift region upon reverse bias can be achieved when those p-islands are arranged in a honeycomb shape. As the lateral superjunction layer gets thinner, the combined effect of superjunction and RESURF makes the optimization more complicated and the benefit of the SJ-structure is compromised.

A 16–28-W 92.8%-Efficiency Monolithic Quasi-Resonant LED Driver With Constant-Duty-Ratio Frequency Regulator

This brief presents a monolithic high-voltage light-emitting diode (LED) driver for lighting applications. The LED driver is able to operate at high switching frequency because large switching loss is eliminated by zero-voltage switching. Inductor values are therefore reduced. A constant-duty-ratio frequency regulator (CDFR) is proposed to regulate the LED current, and the small signal characteristics of the proposed LED driver with CDFR are analyzed. The proposed design, including the controller and power transistor, was fabricated in MagnaChip 0.35-μm 700-V bipolar-CMOSLDMOS process. The LED driver with 2 × 3.9 μH inductors switches at around 5.4 MHz and powers up 16-28 1-W LEDs. Experimental results show that the LED driver achieves peak efficiency of 92.8% within the input voltage range of 55-120 V.

A novel SOI lateral bipolar transistor with 30GHz f/sub max/ and 27V BV/sub CEO/ for RF power amplifier applications

This paper describes a lateral bipolar transistor build on SOI substrate (ie. SOI-LBJT) for RF power amplifier applications. The lateral design concept significantly reduces parasitic resistances and capacitances, and enables very high operating frequency and good trade-off to breakdown voltages. This concept is validated by fabricated SOI-LBJT, which delivers frequency (f/sub t//f/sub max/ = 12/30GHz) and breakdown voltage (BV/sub CEO/=27 V) that approaches the Johnsons limit. This is the first reported Si-BJT that reaches Johnsons limit with BV/sub CEO/ above 10V.

Novel ultra-low power RF Lateral BJT on SOI-CMOS compatible substrate

This work presents a novel ultra-low power RF LBJT on SOI. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-aligned the base contact to the intrinsic base in the 100 nm range. The fabricated LBJTs exhibits superior Johnsons product (fτx BVCEO) in the range between 190-300 GHz.V. The fmaxof the optimal device reaches 46 GHz at collector current density of only 0.15 m/μm2. Both figure-of-merit are in-line with advanced SiGe-HBT device, and superior than previously published data on lateral BJTs. This LBJT is built on SOI-CMOS compatible substrate, and is an ideal candidate for SOI-BiCMOS integration for RF and mixed-signal SoC.

Delay time constant analysis for f/sub /spl tau// optimization in RF Si/SiGe bipolar devices

This work describes an approach for f/sub /spl tau// optimization in RF Si/SiGe bipolar devices by analyzing the delay time components that contribute to the overall transistor speed. Using the proposed parameter extraction method, all delay time constants can be obtained. Subsequently, identifying and minimizing the limiting time delay can effectively improve f/sub /spl tau// of the bipolar devices. Using AKMs Si-BJT technology as a case study, the optimization of the SiGe epitaxial base, intrinsic collector and base doping profiles, and extrinsic collector resistance is demonstrated.

RF bipolar transistors in CMOS compatible technologies

A RF bipolar transistor integrated into a standard 0.35 /spl mu/m CMOS process is presented. This BiCMOS technology features a single-poly NPN transistor with simulated f/sub /spl tau//=16 GHz and BV/sub CEO/=6.4 V. With implanted base and no trench isolation, this device is truly compatible with standard CMOS technology and offers good performance compared to previously published results of BiCMOS technologies.

A RF lateral BJT on SOI for realization of RF SOI-BiCMOS technology

This work presents a lateral RF BJT built on SOI-CMOS compatible substrate. The primary motivation is to realize a SOI-BiCMOS technology suitable for low power RF and mixed-signal SoC. This novel LBJT structure relies on a self-aligned polysilicon side-wall-spacer (PSWS) to connect the base contact to the intrinsic base with dimensions in 100 nm range. The fabricated LBJTs exhibit superior Johnsons product (f/sub /spl tau///spl times/BV/sub CEO/) in the range between 190-300 GHz/spl middot/V. The f/sub max/ of the optimal device reaches 46 GHz at collector current density of only 0.15 mA//spl mu/m/sup 2/. Both figure-of-merits are in-line with advanced SiGe-HBT devices, and superior than previously published data on lateral BJTs.

RF Model of Lateral Bipolar Junction Transistor on Silicon-on-Insulator Substrate

A methodology for modelling a novel highfrequency lateral bipolar junction transistor (LBJT) is described. A modified SPICE-Gummel-Poon (SGP) model is used to simulate the device, with the SGP parameters determined based on the transistors physical geometry. DC, AC, and S-parameter simulations using this model are verified against measured data. The results show good matching and demonstrates that the novel geometry of the LBJT facilitates modelling by reducing the influence of second order effects.