K. Takasuka

Lateral high-speed bipolar transistors on SOI for RF SoC applications

This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental f/sub T//f/sub max/ of the high-speed device are 17/28 GHz, the second fastest reported f/sub T/ for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured f/sub T//f/sub max/ of 12/30 GHz and BV/sub CEO/ of over 25 V produces a Johnsons product well above 300 GHz /spl middot/V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.

Characterizing diodes for RF ESD protection

A diode string as an electrostatic discharge (ESD) protection structure for RF ICs is attractive because of its reduced total parasitic capacitance. This letter reports a comprehensive RF characterization of diodes for RF ESD protection, including S-parameters, parasitic capacitance, and resistance. It is found that a two- or three-diode string may be an optimal RF ESD protection solution due to the balanced overall performance, including ESD protection level, total size, and ESD-induced parasitic effects, etc. An optimized two-diode string for 5 kV ESD protection features a 108.5 fF parasitic capacitance at 2.4 GHz, and is 3680 /spl mu/m/sup 2/ in size. The design was implemented in a commercial 0.35-/spl mu/m BiCMOS technology.

A digital predictive on-line energy optimization scheme for dc-dc converters

This work presents a novel energy conservation technique based on predicting the load current of a DC-DC converter that may feed a variety of loads, such as speakers and displays. The predicted load cnrrent is used to dynamically adjust the size of the output stage transistors and to switch into PFM mode to maximize the instantaneous converter efficiency. By using a segmented output stage, the trade-off between the gate drive losses and RMS conduction losses can be continuously optimized over the full load current range. The technique relies on the fact that the digital data stream which feeds modern electronic loads can be processed in real-time to predict the load cnrrent without relying on explicit cnrrent sensing or slow steady-state calibration techniques. The experimental prototype includes a digitally controlled 3.6V-to-1.8V DC-DC converter with an integrated segmented power stage IC operating at 4 MHz. A high-fidelity class-D audio amplifier acts as the DC-DC converter load. The results show a good agreement between the digitally predicted and actual DC-DC converter load current. The total energy consumed for three music pieces was reduced by up to 38% using the automatic mode/segment control technique. The fully digital efficiency optimization technique is well suited to future monolithic integration in advanced CMOS processes.

A Novel Orthogonal Gate EDMOS Transistor With Improved

A transistor with an orthogonal gate (OG) electrode is proposed to improve dv/dt capability, reduce the gate-to-drain overlap capacitance (C gd), and improve figure of merit (FOM). The OG has both a horizontal section and a vertical section for MOS gate control. This 30-V device is implemented in a 0.18-mum CMOS-compatible process. Comparing to a conventional extended drain MOSFET transistor with the same voltage rating and device size, four times higher dv/dt capability and 53% improvement in FOM are observed.

dv/dt

A trenched LOCOS process has been applied to a UMOS structure to reduce the gate-to-source overlap capacitance (C_gs). A 40% reduction in C_gs is achieved comparing to conventional UMOS, and the devices specific on- resistance R_on, _sp = 60 mOmegaldrmm² is observed. The improvement in device figure-of-merit (FOM = R_on times Q_g) is about 58%.

Capability and Figure of Merit (FOM)

This paper proposes the combination of adjustable architecture and parameter optimization software, employing a method based on artificial intelligence (AI), to realize an image rejection mixer (IRM) that can enhance its image rejection ratio within a short period of time. The main components of the IRM are 6 Gilbert-cell multipliers. The tail current of each multiplier is adjusted by the optimization software, and the gain and phase characteristics are optimized. This adjustment is conventionally extremely difficult because the 6 tail currents to be adjusted simultaneously are mutually interdependent. In order to execute this adjustment efficiently, we employed a Genetic Algorithm (GA) that is a robust search algorithm that can find optimal parameter settings in a short time. We have successfully developed an IRM chip that has a performance of 71 dB and is suitable for single-chip integration with WCDMA applications.

A 70V UMOS Technology with Trenched LOCOS Process to Reduce Cgs

This paper describes a lateral bipolar transistor build on SOI substrate (ie. SOI-LBJT) for RF power amplifier applications. The lateral design concept significantly reduces parasitic resistances and capacitances, and enables very high operating frequency and good trade-off to breakdown voltages. This concept is validated by fabricated SOI-LBJT, which delivers frequency (f/sub t//f/sub max/ = 12/30GHz) and breakdown voltage (BV/sub CEO/=27 V) that approaches the Johnsons limit. This is the first reported Si-BJT that reaches Johnsons limit with BV/sub CEO/ above 10V.

An Image Rejection Mixer with AI-Based Improved Performance for WCDMA Applications

A transistor with an orthogonal gate electrode is proposed to reduce the gate-to-drain overlap capacitance (Cgd). The orthogonal gate has a horizontal section to provide normal gate control and a vertical section to provide field shaping. This device is implemented in a 0.18 mum 30 V HV-CMOS process. Comparing to a conventional EDMOS with the same voltage and size, a 75% Cgd reduction is observed. The Figure-of-Merit (FOM) is improved by 37.5%.

A novel SOI lateral bipolar transistor with 30GHz f/sub max/ and 27V BV/sub CEO/ for RF power amplifier applications

We report the observation and utilization of boron segregation in trench MOSFETs (UMOS) to reduce on-resistance. A trenched LOCOS process has been applied to a UMOS structure to reduce the gate-to-source overlap capacitance (C gs), and it is observed that not only 40% reduction in C gs is achieved but also 45% reduction in specific on-resistance (R on, sp). Figure of merit is improved by 58%. TSUPREM-4 doping profile simulation at the silicon and oxide interface revealed the presence of boron segregation. On-resistance reduction is attributed by the shortened vertical channel length due to boron segregation.

A 30V EDMOS with Orthogonal Gate Structure Based on a 0.1μm CMOS Technology

In this paper, a floating RESURF EDMOS (BV = 55 V, Ron,sp = 36.5 mOmegamiddotmm2) with 45% increased ruggedness and 400% enhanced safe operating area (SOA) is discussed and compared to the conventional EDMOS structure. The proposed EDMOS has both drain and source engineering to enhance device ruggedness, not only via reducing the base resistance of the parasitic bipolar transistor, but also suppressing the base current of the parasitic bipolar transistor at high VGS and high VDS situations, which will also improve the device SOA. Furthermore, the buried deep Nwell allow the device to have better tradeoff between breakdown voltage and on-resistance.