Ian Don Booker

Coherent control of single spins in silicon carbide at room temperature

Spins in solids are cornerstone elements of quantum spintronics. Leading contenders such as defects in diamond or individual phosphorus dopants in silicon have shown spectacular progress, but either lack established nanotechnology or an efficient spin/photon interface. Silicon carbide (SiC) combines the strength of both systems: it has a large bandgap with deep defects and benefits from mature fabrication techniques. Here, we report the characterization of photoluminescence and optical spin polarization from single silicon vacancies in SiC, and demonstrate that single spins can be addressed at room temperature. We show coherent control of a single defect spin and find long spin coherence times under ambient conditions. Our study provides evidence that SiC is a promising system for atomic-scale spintronics and quantum technology.

Influence of Large-Aspect-Ratio Surface Roughness on Electrical Characteristics of AlGaN/AlN/GaN HFETs

The effect of large-aspect-ratio surface roughness of AlGaN/GaN wafers is investigated. The roughness has a surface morphology consisting of hexagonal peaks with maximum peak-to-valley height of more than 100 nm and lateral peak-to-peak distance between 25 and 100 μm. Two epitaxial wafers grown at the same time on SiC substrates having different surface orientation and with a resulting difference in AlGaN surface roughness are investigated. Almost no difference is seen in the electrical characteristics of the materials, and the electrical uniformity of the rough material is comparable to that of the smoother material. The reliability of heterostructure field-effect transistors from both materials have been tested by stressing devices for up to 100 h without any significant degradation. No critical effect, from the surface roughness, on device fabrication is experienced, with the exception that the roughness will directly interfere with step-height measurements.

Comparison of Post-Growth Carrier Lifetime Improvement Methods for 4H-SiC Epilayers

We compare two methods for post-growth improvement of bulk carrier lifetime in 4H-SiC: dry oxidations and implantations with either 12C or 14N, followed by high temperature anneals in Ar atmosphere. Application of these techniques to samples cut from the same wafer/epilayer yields 2- to 11-fold lifetime increases, with the implantation/annealing technique shown to give greater maximum lifetimes. The maximum lifetimes reached are ~5μs after 12C implantation at 600°C and annealing in Ar for 180 minutes at 1500°C. Higher temperatures give decreased lifetimes, a result which differs from reports in literature.

The Role of Chlorine during High Growth Rate Epitaxy

The influence of chlorine has been investigated for high growth rates of 4H-SiC epilayers on 4o off-cut substrates. Samples were grown at a growth rate of approximately 50 and 100 μm/h and various Cl/Si ratios. The growth rate, net doping concentration and charge carrier lifetime have been studied as a function of Cl/Si ratio. This study shows some indications that a high Cl concentration in the growth cell leads to less availability of Si during the growth process.

On-Axis Homoepitaxial Growth of 4H-SiC PiN Structure for High Power Applications

We demonstrate on-axis homoepitaxial growth of 4H-SiC(0001) PiN structure on 3-inch wafers with 100% 4H polytype in the epilayer excluding the edges. The layers were grown with a thickness of 105 µm and controlled n-type doping of 4 x 1014 cm-3.The epilayers were completely free of basal plane dislocations, in-grown stacking faults and other epitaxial defects, as required for 10 kV high power bipolar devices. Some part of the wafer had a lifetime enhancement procedure to increase lifetime to above 2 s using carbon implantation. An additional step of epilayer polishing was adapted to reduce surface roughness and implantation damage.

Donor and double-donor transitions of the carbon vacancy related EH6∕7 deep level in 4H-SiC

Using medium- and high-resolution multi-spectra fitting of deep level transient spectroscopy (DLTS), minority carrier transient spectroscopy (MCTS), optical O-DLTS and optical-electrical (OE)-MCTS measurements, we show that the EH6∕7 deep level in 4H-SiC is composed of two strongly overlapping, two electron emission processes with thermal activation energies of 1.49 eV and 1.58 eV for EH6 and 1.48 eV and 1.66 eV for EH7. The electron emission peaks of EH7 completely overlap while the emission peaks of EH6 occur offset at slightly different temperatures in the spectra. OE-MCTS measurements of the hole capture cross section σp0(T) in p-type samples reveal a trap-Auger process, whereby hole capture into the defect occupied by two electrons leads to a recombination event and the ejection of the second electron into the conduction band. Values of the hole and electron capture cross sections σn(T) and σp(T) differ strongly due to the donor like nature of the deep levels and while all σn(T) have a negative tempe...

Oxidation Induced ON1, ON2a/b Defects in 4H-SiC Characterized by DLTS

The deep levels ON1 and ON2a/b introduced by oxidation into 4H-SiC are characterized via standard DLTS and via filling pulse dependent DLTS measurements. Separation of the closely spaced ON2a/b defect is achieved by using a higher resolution correlation function (Gaver-Stehfest 4) and apparent energy level, apparent electron capture cross section and filling pulse measurement derived capture cross sections are given.

Comparison of Carrier Lifetime Measurements and Mapping in 4H SiC Using Time Resolved Photoluminscence and μ-PCD

Carrier lifetime measurements and wafer mappings have been done on several different 4H SiC wafers to compare two different measurement techniques, time-resolved photoluminescence and microwave induced photoconductivity decay. The absolute values of the decay time differ with a factor of two, as expected from recombination and measurement theory. Variations within each wafer are comparable with the two techniques. Both techniques are shown to be sensitive for substrate quality and distribution of extended defects.

Influence of Growth Temperature on Carrier Lifetime in 4H-SiC Epilayers

Carrier lifetime and formation of defects have been investigated as a function of growth temperature in n-type 4H-SiC epitaxial layers, grown by horizontal hot-wall CVD. Emphasis has been put on having fixed conditions except for the growth temperature, hence growth rate, doping and epilayer thickness were constant in all epilayers independent of growth temperature. An increasing growth temperature gave higher Z1/2 concentrations along with decreasing carrier lifetime. A correlation between growth temperature and D1 defect was also observed.

The Effect of Growth Conditions on Carrier Lifetime in N-Type 4H-SiC Epitaxial Layers

Carrier lifetime has been studied as a function of C/Si ratio and growth rate during epitaxial growth of n-type 4H-SiC using horizontal hot-wall CVD. Effort has been put on keeping all growth parameters constant with the exception of the parameter that is intended to vary. The carrier lifetime is found to decrease with increasing growth rate and the highest carrier lifetime is found for a C/Si ratio of 1. The surface roughness was correlated with epitaxial growth conditions with AFM analysis.