Louise Lilja

Improved Epilayer Surface Morphology on 2˚ Off-Cut 4H-SiC Substrates

Homoepitaxial layers of 4H-SiC were grown with horizontal hot-wall CVD on 2˚ off-cut substrates, with the purpose of improving the surface morphology of the epilayers and reducing the density of surface morphological defects. In-situ etching conditions in either pure hydrogen or in a mixture of silane and hydrogen prior to the growth were compared as well as C/Si ratios in the range 0.8 to 1.0 during growth. The smoothest epilayer surface, together with lowest defect density, was achieved with growth at a C/Si ratio of 0.9 after an in-situ etching in pure hydrogen atmosphere.

On-Axis Homoepitaxial Growth of 4H-SiC PiN Structure for High Power Applications

We demonstrate on-axis homoepitaxial growth of 4H-SiC(0001) PiN structure on 3-inch wafers with 100% 4H polytype in the epilayer excluding the edges. The layers were grown with a thickness of 105 µm and controlled n-type doping of 4 x 1014 cm-3.The epilayers were completely free of basal plane dislocations, in-grown stacking faults and other epitaxial defects, as required for 10 kV high power bipolar devices. Some part of the wafer had a lifetime enhancement procedure to increase lifetime to above 2 s using carbon implantation. An additional step of epilayer polishing was adapted to reduce surface roughness and implantation damage.

Fast Growth Rate Epitaxy on 4° Off-Cut 4-Inch Diameter 4H-SiC Wafers

We report the development of over 100 μm/h growth rate process on 4-inch diameter wafers using chlorinated growth. The optimized growth process has shown extremely smooth epilayers completely free of surface step-bunching with very low surface defect density, high uniformity in thickness and doping and high run to run reproducibility in growth rate, controlled doping and defect density.

Oxidation Induced ON1, ON2a/b Defects in 4H-SiC Characterized by DLTS

The deep levels ON1 and ON2a/b introduced by oxidation into 4H-SiC are characterized via standard DLTS and via filling pulse dependent DLTS measurements. Separation of the closely spaced ON2a/b defect is achieved by using a higher resolution correlation function (Gaver-Stehfest 4) and apparent energy level, apparent electron capture cross section and filling pulse measurement derived capture cross sections are given.

Comparison of Carrier Lifetime Measurements and Mapping in 4H SiC Using Time Resolved Photoluminscence and μ-PCD

Carrier lifetime measurements and wafer mappings have been done on several different 4H SiC wafers to compare two different measurement techniques, time-resolved photoluminescence and microwave induced photoconductivity decay. The absolute values of the decay time differ with a factor of two, as expected from recombination and measurement theory. Variations within each wafer are comparable with the two techniques. Both techniques are shown to be sensitive for substrate quality and distribution of extended defects.

Influence of Growth Temperature on Carrier Lifetime in 4H-SiC Epilayers

Carrier lifetime and formation of defects have been investigated as a function of growth temperature in n-type 4H-SiC epitaxial layers, grown by horizontal hot-wall CVD. Emphasis has been put on having fixed conditions except for the growth temperature, hence growth rate, doping and epilayer thickness were constant in all epilayers independent of growth temperature. An increasing growth temperature gave higher Z1/2 concentrations along with decreasing carrier lifetime. A correlation between growth temperature and D1 defect was also observed.

The Effect of Growth Conditions on Carrier Lifetime in N-Type 4H-SiC Epitaxial Layers

Carrier lifetime has been studied as a function of C/Si ratio and growth rate during epitaxial growth of n-type 4H-SiC using horizontal hot-wall CVD. Effort has been put on keeping all growth parameters constant with the exception of the parameter that is intended to vary. The carrier lifetime is found to decrease with increasing growth rate and the highest carrier lifetime is found for a C/Si ratio of 1. The surface roughness was correlated with epitaxial growth conditions with AFM analysis.

Influence of n-type doping levels on carrier lifetime in 4H-SiC epitaxial layers

In this study we have grown thick 4H-SiC epitaxial layers with different n-type doping levels in the range 1E15 cm-3 to mid 1E18 cm-3, in order to investigate the influence on carrier lifetime. The epilayers were grown with identical growth conditions except the doping level on comparable substrates, in order to minimize the influence of other parameters than the n-type doping level. We have found a drastic decrease in carrier lifetime with increasing n-type doping level. Epilayers were further characterized with low temperature photoluminescence and deep level transient spectroscopy.

Smooth 4H-SiC Epilayers Grown with High Growth Rates with Silane/Propane Chemistry Using 4° Off-Cut Substrates

4H-SiC epilayers with very smooth surfaces were grown with high growth rates on 4° off-cut substrates using standard silane/propane chemistry. Specular surfaces with RMS values below 0.2 nm are presented for epilayers grown with growth rates up to 30 μm/h using horizontal hot-wall chemical vapor deposition, with up to 100 μm thickness. Optimization of in-situ etching conditions and C/Si ratio are presented.

Radial Variation of Measured Carrier Lifetimes in Epitaxial Layers Grown with Wafer Rotation

In this report we present homoepitaxial growth of 4H-SiC on the Si-face of nominally on-axis substrates with diameter up to 100 mm in a hot-wall chemical vapor deposition reactor. A comparatively low carrier lifetime has been observed in these layers. Also, local variations in carrier lifetime are different from standard off-cut epilayers. The properties of layers were studied with more focus on charge carrier lifetime and its correlation with starting growth conditions, in-homogeneous surface morphology and different growth mechanisms.