Ichiro Hazeyama

Real chip size three-dimensional stacked package

As mobile electronics products become more compact and lighter and perform better, the need to decrease the number of large-scale integration (LSI) packages mounted on each board as well as decreasing their mounting area is increasing. This paper describes a newly developed ultrahigh-density three-dimensional (3-D) stacked package called a flexible carrier folded real chip size package (FFCSP). The FFCSP is constructed by stacking very thin single chip packages of real chip size on top of one another. Each single chip package consists of an LSI chip and a small piece of flexible printed circuit (FPC), which has an insulating layer made of thermoplastic resin. The FFCSPs advantages are its ultrasmall size, thinness, highly flexible assembly, and a good test yield compared with conventional 3-D stacked packages. The FFCSP will enable the future miniaturization and raise the functionality of the next wave of mobile electronics products.

Low firing temperature silicon oxide for microwave substrate

A novel material for making microwave substrates has been developed. The material is silicon oxide, which has a low dielectric constant (/spl epsi/r=5.0-5.2 at 10-20 GHz) and a low loss tangent (tan/spl delta/=8.3/spl times/10/sup -4/-9.1-10/sup -4/ at 10-20 GHz). The new process makes sintering of this silicon oxide possible at low temperature (below 1000/spl deg/C). Consequently, substrates consisting of this silicon oxide are capable of forming copper conductors by cofiring. The key technologies of this process are using amorphous silicon oxide powder that has a particle diameter of the nanometer order, and firing in an atmosphere containing water. Additionally, a multilayer substrate was developed by applying a green sheet lamination technique.

Flip chip bonding reliability of advanced glass ceramic chip size package

In order to realize high-density wiring and to increase the reliability of chip interconnection to printed wiring boards (PWBs), we have developed glass ceramic chip size packages (CSPs). A 64M-DRAM chip was connected to the glass ceramic substrate via Au bumps by a flip chip bonding technique with high interconnection reliability, and the substrate was mounted on a PWB via solder ball bumps. To evaluate the reliability of the glass ceramic CSP, a thermal stress simulation was performed and the analysis indicated that thin glass ceramic CSPs were highly reliable. This finding was supported by thermal cycle testing using actual glass ceramic CSPs and identically structured alumina CSPs. The thin glass ceramic CSPs passed 1000 cycles, although failures were detected on the alumina CSPs between 500 and 1000 cycles. These failures were analyzed and it was confirmed that fatigue fractures occurred in the solder ball bumps due to coefficient of thermal expansion (CTE) mismatch and substrate rigidity.