Keiichiro Kata

Simple-structure, generally applicable chip-scale package

One way to provide the ultimate shrinkage, required for the fabricating of small, lightweight, and high-performance electrical devices is by using chip-scale packaging. We have therefore developed an original chip-scale package called fine-pitch BGA (FPBGA), which has a very simple structure, consisting of carrier tape, an adhesive layer, and solder bumps. Its assembly process is similar to that of TCP assembly, and FPBGA has many advantages over other IC mounting processes and other similar chip-scale packages.

Real chip size three-dimensional stacked package

As mobile electronics products become more compact and lighter and perform better, the need to decrease the number of large-scale integration (LSI) packages mounted on each board as well as decreasing their mounting area is increasing. This paper describes a newly developed ultrahigh-density three-dimensional (3-D) stacked package called a flexible carrier folded real chip size package (FFCSP). The FFCSP is constructed by stacking very thin single chip packages of real chip size on top of one another. Each single chip package consists of an LSI chip and a small piece of flexible printed circuit (FPC), which has an insulating layer made of thermoplastic resin. The FFCSPs advantages are its ultrasmall size, thinness, highly flexible assembly, and a good test yield compared with conventional 3-D stacked packages. The FFCSP will enable the future miniaturization and raise the functionality of the next wave of mobile electronics products.

Large scale multilayer glass-ceramic substrate for supercomputer

A large-scale multilayer glass-ceramic (MGC) substrate, which has a low dielectric constant

Fabrication of controlled porosity in a tape cast glass ceramic substrate material

Abstract Isolated porosity was formed in a glass ceramic substrate body by the volatilization of polymer spheres prior to sintering. The glass ceramic samples were fabricated by both pellet and tape cast processes. The dielectric constant and loss were measured over a frequency range of 200 Hz to 9.3 GHz, at room temperature. The dielectric constant was reduced and the loss remained satisfactory.

High-performance FCBGA based on multi-layer thin-substrate packaging technology

Abstract We developed a new concept flip-chip ball grid array (FCBGA) based on multi-layer thin-substrate (MLTS) packaging technology in order to meet the strong demand for high-density, high-performance, and low-cost LSI packages. The most important feature of MLTS packaging is that, only a high-density and high-performance MLTS remains by removing the metal plate after mounting an LSI chip. The MLTS packaging offers the advantages of (1) good registration accuracy, which makes higher-density and finer-pitch pattering possible; (2) an ideal multi-layer structure that is highly suitable for high-speed and high-frequency applications; (3) excellent flip-chip mounting reliability, which makes higher-pin-count and finer-pitch area array flip-chip interconnection possible; (4) excellent reliability, supported by use of high T g (glass transition temperature) resin; and (5) a cost-effective design achieved as a result of fewer layers fabricated with fine-pitch patterning. We successfully produced a high-performance FCBGA prototype based on our MLTS packaging technology. The prototype comprises an LSI chip connected to approximately 2500 bonding pads arranged in 240 μm pitch area array, and 1296 I/O pads for BGA. The prototype FCBGA’s excellent long-term reliability was demonstrated through a series of tests conducted on it.

Inner bump bonding technology for CSP

D/sup 2/BGA (die dimension BGA) is an NEC CSP, consisting of die, flexible printed circuit tape, resin, solder bumps and reinforcement resin. Assembly consists of bonding, lamination, encapsulation, solder ball placement and singulation. The bonding technique uses IBB (inner bump bonding) technology. IBB is similar to ILB (inner lead bonding), using an ultrasonic thermocompression single point bonder for TAB. Instead of the TAB inner lead, inner bumps are bonded to an Al pad. The polyimide film is drilled on the Cu trace by laser ablation. The inner bumps are made of an electrodeposited Cu core and Au plating. Various factors affected the Al-Au intermetallic bond: (1) inner bump shape; (2) inner bump deformation; (3) polyimide base film thickness; and (4) the adhesive properties. The Au layer deformation ratio was one of the most important factors; in the three bonded parts, the Au layer, Cu core and Cu trace, Au layer deformation affected bonding quality most significantly. A lower Au layer deformation ratio resulted in poorer bonding. A low Cu core deformation ratio resulted in a high Au layer deformation ratio and gave a good intermetallic bond between the Au plated Cu bump and the Al pad. Flexible PC tape had a thermoplastic polyimide adhesive layer on the die side, and the bonding area was reinforced by the adhesive layer during the bonding operation. The adhesive properties were also found to affect the intermetallic bond. Lower adhesive strength caused damage to the Al pad or Si chip during bonding. Strong flexible PC tape-die surface adhesion resulted in highly reliable bonding.

Development of molded fine-pitch ball grid array (FPBGA) using through-hole bonding process

A molded fine-pitch ball grid array (FPBGA) structure, consisting of the fabricated chip, carrier tape, molded resin, and solder bumps, has many advantages over conventional structures for chip-scale packages. The assembly process of FPBGA consists of through-hole bonding, lamination, molding, solder bump formation, and outline cutting. The bonding process, which is called through-hole bonding, does not have lead bending or wire or lead crossing and allows a finer chip pad pitch to be used. However, since it is difficult to evaluate the bonding strength of each part, unlike wire bonding or TAB inner lead bonding, we developed several methods for evaluating the through-hole bonding. In the fabrication of molded FPBGA, the back side of the chip is molded by resin, which improves the robustness of the package. In this process, it is important to keep coplanarity of the package surface. We are currently testing the reliability of the molded FPBGA and results are good.

Low dielectric constant new materials for multilayer ceramic substrate

A low-dielectric-constant glass-ceramic material system with improved thermal expansion coefficient and flexural strength is described. This material system consists of quartz glass, cordierite, and borosilicate glass. It can be sintered at temperatures below 1000 degrees C, making it possible to use low-electrical-resistivity conductors, for example, Au, Ag, Ag-Pd, and Cu, as signal lines and interconnections. A dielectric constant in the 3.9 to 4.7 range can be realized. The thermal expansion coefficient can be controlled to match that of the chips carried. The flexural strength (2000 kg/cm/sup 2/) is relatively high. Using green-sheet-lamination technology, a low-dielectric-constant multilayer glass-ceramic substrate with Ag-Pd wiring, suitable for use as a substrate for a high-speed VLSI multichip package, was developed.<<ETX>>