Ichiro Koiwa

Reduction of Process-induced Damage and Improvement of Imprint Characteristics in SrBi2Ta2O9 Capacitors by Postmetallization Annealing

We investigated the effect of process damage induced after capacitor etching procedures in the process of ferroelectric random access memory (FeRAM) fabrication for SrBi2Ta2O9 capacitors. We found that this damage was suppressed by postmetallization annealing (400 ?C, 30 min in O2) and that imprint characteristics were improved by the annealing, because active elements such as hydrogen and water induced during contact hole formation on tungsten plugs and first-metal formation are adsorbed effectively by the annealing before they penetrate into these capacitors.

Effects of bottom electrode conditions on ferroelectric properties of SrBi2Ta2O9 thin films

The effect of adhesion layers under the bottom electrodes on ferroelectric characteristics of SrBi2Ta2O9 (SBT) thin films synthesized by sol-gel method was investigated. The remanent polarization (2Pr) of SBT films was found to be smaller for the tantalum oxide (TaOx) adhesion layer than for the titanium oxide (TiOx) adhesion layer, whereas the coercive voltage (2Vc) was larger for the TaOx adhesion layer than for the TiOx adhesion layer. The difference was due to a larger c-axis distribution of crystals in the SBT film on Pt with the TaOx layer than with the TiOx layer. Moreover, the imprint characteristics of SBT capacitors on the TaOx layer were better than those on the TiOx layer because the 2Vc in SBT capacitors was larger for the TaOx layer than for the TiOx layer, and the polarization stability against the hysteresis shift was better for the TaOx layer than for the TiOx layer.

Effects of Storage Conditions on Imprint Characteristics in SrBi2Ta2O9 Capacitors

The effects on the imprint characteristics of SrBi2Ta2O9 capacitors of various storage conditions were investigated. It was observed that the hysteresis shifts due to imprint degradations were smaller in the case in which the both electrodes of the capacitors were connected after increasing the temperature of the capacitors that were polarized at room temperature than in the case in which the electrodes were not connected. The acceleration ratio (Racc) of the slope of the hysteresis shift in the capacitors without connected electrodes to that with connected electrodes is 1.35 at 125 °C in device-size capacitors, and the ratio is much less dependent on temperature than the hysteresis shift. Moreover, it was also found that Racc was smaller in the case in which the process-induced damage located near the interfaces was larger.

Analyses of plated films by thermal desorption spectrometry (TDS)

Abstract Thermal desorption spectrometry (TDS) is an effective method to detect gases that are trapped in films, and it has been used in the semiconductor field. In this paper, there are two main purposes. One is the detection of toxic elements such as lead, which are contained in extremely small quantities in plated films, especially for electroless Ni–P alloy films as bath stabiliser. The other is the detection of gases such as hydrogen, which is a key factor to control film properties, especially for Cu electroplating. Lead has been used for electroless Ni–P films as stabiliser; recently, bismuth has also been used as stabiliser instead of lead from the viewpoint of environment safety and restriction of hazardous substances. The TDS has detected both lead and bismuth contained in electroless Ni–P films, which have been plated from baths containing only 0·1 ppm of Pb and Bi. Copper electroplating has been used to produce printed circuit boards and recently to produce semiconductor wiring. To fill via holes, several kinds of additives, three or more, have been added into the plating bath. The TDS is effective to detect the captured materials because it detects all kinds of mass from 1 to more than 100. Moreover, this method is used for both qualitative and quantitative analyses. In this study, the kinds of additives greatly affected captured materials, kinds and quantity. Three kinds of additives were added in the bath. The film plated from the bath containing only polyethylene glycol with chloride ion showed the lowest hydrogen desorption level; the film plated from the bath containing only bis(3-sulfopropyl)disulfide (SPS) showed the highest level. However, the film plated from the bath that contained only SPS showed the lowest sulphur oxide level. On the other hand, the film plated from the bath containing only Janus green B and the plated bath without additives showed middling levels. The film plated from the bath with all additives showed the highest water desorption level and the lowest hydrogen desorption level, and its contained condition was strongly dependent on the additives.

SiP fabricated by W-CSP using excimer laser via-hole formation and Cu electroplating

Recently high density packaging technologies have been strongly requested to realize ubiquitous networking society. A wafer-level chip size packaging (W-CSP) technology is one of the most promising technologies for high density and environmental friendly packaging. Purpose of this study is to fabricate system in package (SiP) by using W-CSP technology. In this study, we have fabricated two chip module by W-CSP using excimer laser to form via-holes and electro-plating to fill via-holes. This study has two main new technologies, one is new via-hole formation by using excimer laser that makes small (30µm diameter) and deep (50 and 100µm) via-holes, a micro-lens array has been used to shorten via-hole formation time. The micro-lens array makes one-line via-hole formation at once. And the other is new copper electroplating techniques to fill via-holes which have same diameter (30µm) and different depth (50 and 100µm) by controlling additives and agitating conditions. In this study, we have fabricated two chip module, first step, second chip mounting on first chip. The second chips whose thickness was 50 µm was mounted on wafer (first chip) that has been finished up wafer process. The second chips have been thinned and mounted by DAF tape. Next, polyimide or epoxy resin whose thickness was about 100 µm was coated by spin-coater to cover the mounted chips. Two types of viahole whose depths were different, 50 and 100 µm, should be formed by excimer laser to connect pads between the wafer pad and mounted chip pad. The excimer laser have formed two types of via whose diameter was about 30 µm. Damage by excimer laser irradiation have been examined by irradiation of laser to gate of FET transistor directly. Properties of FET transistor did not change even after 500 pluses of 400 mJ/cm2 which are much enough for via-hole formation. To shorten via-hole formation time, a micro-lens array was designed. An ashing process with CF4 gas has performed to clean surface and inside of via-holes. After via-hole formation, seed-layers, sputtered Ti and Cu films are necessary for following copper electro-deposition. By microscopy measurement, the seed-layers were uniformly formed from top to bottom of via-hole. In general mixture of additives, these are brightener, leveler and suppressor, made via-hole filling completely. By controlling leveler effect, the via-hole with 30 µm diameter and 100 µm depth have been perfectly filled by copper electroplating. Both mechanical agitation and current density is effective to via-hole filling. Moreover, additional electroless copper seed-layer to increase conductivity at near the bottom of via-hole is also effective to suppress voids at the bottom of vai-holes. Therefore, the multi-chip module would be performed by the W-CSP with excimer laser and copper electro-plating.

Selective deposition on electrodes of chip component by electroless plating method

The selective electroless deposition on metallic electrodes of a micro-passive-chip component was investigated. We performed three pretreatments: (a) alkaline degreasing, (b) acid activation, and (c) catalytic activation by the double alternate-dipping method consisting of two steps, i.e., sensitization (SnCl2) and activation (PdCl2). Catalytic conditions such as the concentration of PdCl2, activation time, and number of activation times were optimized to achieve the selectivity of electroless deposition. The mechanism of the selectivity of electroless deposition was investigated by X-ray photoelectron spectroscopy measurements. Tetravalent Sn and metallic Pd are observed on the inner electrode of the sample. On the other hand, metallic Sn and tetravalent Pd are mainly observed in certain areas except the inner electrode areas. These results indicate that the sensitization is performed well in the inner electrode region because Pd must be in a metallic state to validate its catalytic activity.

Low-κ Materials and Development Trends

Though low-κ materials have been actively investigated by many researchers, target values of ITRS (International Technology Roadmap for Semiconductor) have not achieved. To reduce RC delay, both lower resistance wiring material, copper, and low-κ material are necessary. Especially for recent IC chips, ratio of BEP (Back End Process) has rapidly increased with increasing wiring layers. This chapter reviews low-κ materials and proposes future development.