Kinya Ashikaga

Submicron Ferroelectric Capacitors Fabricated by Chemical Mechanical Polishing Process for High-Density Ferroelectric Memories

Submicron ferroelectric capacitors were fabricated by a damascene process using chemical mechanical polishing (CMP). The fabricated capacitors consisted of SrBi2Ta2O9 (SBT) film with top and bottom electrodes of IrO2 films. The capacitor size was 0.8 µm in diameter, that is, 0.5 µm2 in area. Damage by the fabrication process was not observed in electrical measurements, such as the dependence of remanent polarization on electric field and leakage current properties. The remanent polarization (2Pr) of 5 µC/cm2 at the saturation voltage of 2 V is half that of a large capacitor because the SBT films were composed of single-crystal grains in the bismuth-layered perovskite structure and micro-crystals in many phases including pyrochlore. The crystallinity of the SBT films may be associated with the redistribution of Bi between the SBT thin films and the IrO2 electrodes during the crystallization annealing of SBT.

Analysis of memory retention characteristics of ferroelectric field effect transistors using a simple metal–ferroelectric–metal–insulator–semiconductor structure

Memory retention characteristics of metal–ferroelectric–metal–insulator–semiconductor (MFMIS) field effect transistors (FETs) were investigated in detail using a simple structure, referred to as quasi-MFMIS, in which one electrode of the metal–ferroelectric–metal (MFM) capacitor is connected to a gate electrode of a conventional metal–oxide–semiconductors (MOS) FET using an external interconnection cable. It was found that the memory window of the MFMIS FET was quickly lost (after about 1000 s) and from a comparison with simulations, this was attributed mainly to a decrease in ferroelectric polarization due to a depolarization field inevitably remaining in the ferroelectric film during memory retention.

Reduction of Process-induced Damage and Improvement of Imprint Characteristics in SrBi2Ta2O9 Capacitors by Postmetallization Annealing

We investigated the effect of process damage induced after capacitor etching procedures in the process of ferroelectric random access memory (FeRAM) fabrication for SrBi2Ta2O9 capacitors. We found that this damage was suppressed by postmetallization annealing (400 ?C, 30 min in O2) and that imprint characteristics were improved by the annealing, because active elements such as hydrogen and water induced during contact hole formation on tungsten plugs and first-metal formation are adsorbed effectively by the annealing before they penetrate into these capacitors.

Effects of bottom electrode conditions on ferroelectric properties of SrBi2Ta2O9 thin films

The effect of adhesion layers under the bottom electrodes on ferroelectric characteristics of SrBi2Ta2O9 (SBT) thin films synthesized by sol-gel method was investigated. The remanent polarization (2Pr) of SBT films was found to be smaller for the tantalum oxide (TaOx) adhesion layer than for the titanium oxide (TiOx) adhesion layer, whereas the coercive voltage (2Vc) was larger for the TaOx adhesion layer than for the TiOx adhesion layer. The difference was due to a larger c-axis distribution of crystals in the SBT film on Pt with the TaOx layer than with the TiOx layer. Moreover, the imprint characteristics of SBT capacitors on the TaOx layer were better than those on the TiOx layer because the 2Vc in SBT capacitors was larger for the TaOx layer than for the TiOx layer, and the polarization stability against the hysteresis shift was better for the TaOx layer than for the TiOx layer.

Effects of Storage Conditions on Imprint Characteristics in SrBi2Ta2O9 Capacitors

The effects on the imprint characteristics of SrBi2Ta2O9 capacitors of various storage conditions were investigated. It was observed that the hysteresis shifts due to imprint degradations were smaller in the case in which the both electrodes of the capacitors were connected after increasing the temperature of the capacitors that were polarized at room temperature than in the case in which the electrodes were not connected. The acceleration ratio (Racc) of the slope of the hysteresis shift in the capacitors without connected electrodes to that with connected electrodes is 1.35 at 125 °C in device-size capacitors, and the ratio is much less dependent on temperature than the hysteresis shift. Moreover, it was also found that Racc was smaller in the case in which the process-induced damage located near the interfaces was larger.

Dependences of Process-Induced Damage on Imprint Characteristics in SrBi2Ta2O9 Capacitors

We investigated hysteresis shifts in SrBi2Ta2O9 capacitors during high-temperature storage in an attempt to understand the mechanism underlying imprint degradation. We found that the activation energy (Ea) of imprint degradation is derived from the temperature dependence of the hysteresis shift, but is almost independent of the size of the capacitors (about 0.2 eV). On the other hand, Ea is strongly dependent on the size of contact areas on the upper electrodes of the capacitors (0.1 to 0.2 eV). This result suggests that imprint degradation is mainly due to the characteristics of ferroelectric-electrode interfaces, and is not due to the edges of the capacitors. We reached this conclusion because the dependence on the contact areas is related to process-induced damage near the upper electrode.

Improvement of crystallinity of epitaxial Si1−xGex films with SiH4 treatment in in-situ rapid thermal chemical vapor deposition

Improvements in the crystallinity of epitaxial Si1−xGex films have been investigated by treating Si substrates with SiH4 in rapid thermal chemical vapor deposition (RTCVD) to bring this technology close to manufacture. It is found that the epitaxial Si layer formed during the SiH4 treatment just before Si1−xGex deposition is effective for improving the crystal quality of epitaxial Si1−xGex films. This method is seen as a promising technology for realizing heterostructural devices using Si1−xGex films.

Novel Epitaxial Growth Technology of Si1-xGex Films by in situ Rapid Thermal Chemical Vapor Deposition

In the future generation of Si-based heterostructural devices such as heterobipolar transistor (HBT), epitaxial Si 1-;Ge; film becomes of great importancel)2). The electrical characteristics and reliability of the devices will critically depend on the perfection of the epitaxial layer. Thus, the goal of the epitaxial growth of Sil-xGex is to obtain the film with controlled Ge concentration and abrupt dopant profiles, and free from dislocation. Considering commensuration with manufacture and advantage of forming abrupt profiles of dopant and Ge content, we have studied the epitaxial growth of Si1-1Ge; using RTCVD. It is, in general, recognized that surface cleaning or etching has great influence on epitaxy. For instance, high temperature baking in H2 or HCI etching is often used. However, by these methods, the surface may become rough. Thus, in this paper, we will propose a novel epitaxial technology which is effective for decreasing dislocation and smoothing Si1-;Ge; film surface. We will also demonstrate some results of in situ boron doping using BZH6 gas by RTCVD.