Ido Dolev

Advanced lithography: wafer defect scattering analysis at DUV

Considerable effort is directed towards the development of next-generation lithography processes, addressing the need for transistor densification to meet Moores Law. The aggressive design rule shrinkage requires very tight process windows and induces various types of pattern failure with lithography process variations. Since the lithography process is critical in the wafer fabrication process, the requirements for high sensitivity defect detection in the lithography process becomes tighter as design rules shrink. Analysis of the root cause of the defects and of their interaction with various light sources and optics systems configurations for wafer inspection is essential for understanding the detection limits and requirements from advanced inspection systems targeting future lithography inspection applications. In this work, we present an analysis of wafer defects light scattering and detection for a variety of 3xnm design rule resist structures with various polarizations and optics configurations, at the visible, at UV and at DUV wavelengths. The analysis indicates on the defect scattering and inspection performance trends for a variety of resist structures and defect types, and shows that control of the polarization of the optical inspection system is critical for enhanced scattering and detection sensitivity. The analysis is performed also for the 2xnm and 1xnm design rules showing the advantages of polarized DUV illumination over unpolarized and visible illumination.

Simulating semiconductor structures for next-generation optical inspection technologies

Abstract. We present a technique for optimizing advanced optical imaging methods for nanoscale structures, such as those encountered in the inspection of cutting-edge semiconductor devices. The optimization flow is divided to two parts: simulating light-structure interaction using the finite-difference time-domain (FDTD) method and simulating the optical imaging system by means of its optical transfer function. As a case study, FDTD is used to simulate 10-nm silicon line-space and static random-access memory patterns, with irregular structural protrusions and silicon-oxide particles as defects of interest. An ultraviolet scanning-spot optical microscope is used to detect these defects, and the optimization flow is used to find the optimal imaging mode for detection.

Extending DUV mask inspection tool for inspecting 2xnm HP and beyond

Advanced 193nm DUV optical inspection tools that can cover 2Xnm HP node become more important and they are being tested to estimate their extendibility. We report DUV based inspection results evaluated and compared to wafer prints, as well as mask CD-SEM images in order to determine the size of printable defects that must be detected in each device node. Applied Materials® advanced Aera™ optical mask inspection tool that adapted a new optical technology enhancement was utilized to evaluate its inspection capability. The illumination conditions and pixel size were optimized to increase inspection sensitivity and reach detection requirements for not only critical defects that print on the wafer but also non-printing defects that indicate to a mask issue. Simulation was used to study suitable optical illumination conditions analyzing results to achieve the best performance for high-end EUV mask inspection toward next generation lithography.

Characterization of EUV resists for defectivity at 32nm

Extreme ultraviolet (EUV) lithography is considered as the leading patterning technology beyond the ArF-based optical lithography, addressing the need for transistor densification to meet Moores Law. Theoretically, EUV lithography at 13.5nm wavelength meets the resolution requirements for 1xnm technology nodes. However, there are several major challenges in the development of EUV lithography for mass production of advanced CMOS devices. These include the development of high power EUV light sources, EUV optics, EUV masks, EUV resists, overlay accuracy, and metrology and inspection capabilities. In particular, it is necessary to ensure that effective defect control schemes will be made available to reduce the EUV lithography defectivity to acceptable levels. This paper presents a study on the wafer defectivity and characterization of patterned EUV resists, with the objective of providing a quantitative comparison between the defectivity of different resist materials and different stacks. Patterned wafers were printed using the ASML® EUV full-field Alpha-Demo Tool (ADT 0.25 NA) at imec. The EUV resist patterns were 32nm line/spaces. Several advanced resist types were screened experimentally. The different resist types and stacks were inspected using a DUV laser based brightfield inspection tool, followed by a SEM defect review and CD metrology measurements. The patterns were characterized in terms of defect types and defect density. We identified the major defect types and discuss factors that affect the defectivity level and pattern quality, such as resist type, exposure dose and focus. Defect scattering analysis of DUV polarized light at different polarizations was performed, to indicate on the inspection performance trends for a variety of defect types and sizes of the different resists and stacks. The scattering analysis shows that higher defect scattering is induced using polarized light.

EUV defect characterization study on post litho and etch for 1x and 2x node processes

EUV mask metrology and inspection challenges as well as EUV patterned wafer metrology and inspection strategies must be addressed to enable EUV patterning for pilot and high volume production. In this work we present a defectivity analysis of defects from post EUV lithography and etch and the correlation between them on 40nm and 28nm half pitch (HP) line/space structures. The objective of the work was to study the lithography and etch process window vs. pitch as well as to characterize the performance of a DUV brightfield wafer inspection system on EUV stacks in order to detect EUV related DOIs. In addition to defect characterization for the lithography and etch layers, we present the results of scattering simulation from these layers, with polarized 266nm DUV illumination, to provide insight on the light-pattern interaction and on the critical detection parameters.

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

Inspection sensitivity improvement through optimization of lobe blocking on high-end memory devices

As cell size of advanced memory is approaching to around 50nm hence the size of defect is required to be detected is less than 30nm. In the array area best combinations of the inspection tool that can be achieved the maximum sensitivity through optics based are short wavelength, small pixel and collection from off-axis perspectives when the noise from pattern can be blocked. To remove the pattern noise efficiently and having enough defect signal to detector laser illumination is better approach than broadband lamp where lobe formation is not well defined and light intensity is not high enough. UVisionTM 3D channel which is off-axis collection of light from normal illumination was evaluated on array area of advanced memory design rules. Below 100nm node design rule 3D channel can successfully suppress the Customized Light Collection (CLC) lobes which are diffraction lobes from memory array pattern. In this paper we would like to report significant improvement of defect detection sensitivity through optimizing CLC lobe mask. It was developed to maximize the defect collection area and angle and showed improvements on defect detection through SNR and signal enhancement. Because of CLC lobe suppressions inverse relationship with device design rule the results show that the smaller design rule gives better defect signal detection capability.

Methodical approach to improve defect detection sensitivity on lithography process using DUV inspection system

Adoption of immersion technology to push printing resolution with existing wavelength (193nm) brings to many concerns about defect controls on lithography process. Along with aggressive design rule shrinkage k1 factor of lithography process is close to 0.3 and this low k1 factor process results in very tight process window. Narrow process window easily induces various types of pattern failure with lithography process variation. Therefore requirements of sensitive defect detection on lithography step are grown with the adoption of immersion and low k1 regime processing. Similar to lithography resolution enhancement with shorter wavelength the inspection tool also is required to move forward to shorter wavelength to improve defect sensitivity through resolution improvement and scattering cross section increase. Therefore the main wavelength regime on high end defect inspection system is already shifted to DUV. In this paper, we would like to report improvement of defect detection sensitivity on lithography process inspection through step by step trace of the defect formation and shape. Throughout the process flows till final etch and cleaning process from lithography the SEM non-visible defects or buried defects on lithography step are turned into line open or line thinning which are killer defects and has low defect signal on cleaning step. Also the benefits of DUV inspection system on lithography layer application is discussed through wafer noise suppression from Anti Reflection Coating (ARC) and larger defect signal from effective defect size increasing.