Ik Joon Chang

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. However, due to parameter variations in scaled technologies, stable operation of SRAMs is critical for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs fail to achieve reliable subthreshold operation. Hence, researchers have considered different configuration SRAMs for subthreshold operations having single-ended 8T or 10T bit-cells for improved stability. While these bit-cells improve SRAM stability in subthreshold region significantly, the single-ended sensing methods suffer from reduced bit-line swing due to bit-line leakage noise. In addition, efficient bit-interleaving in column may not be possible and hence, the multiple-bit soft errors can be a real issue. In this paper, we propose a differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability. The proposed bit-cell also provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). For read access, we employ dynamic DCVSL scheme to compensate bitline leakage noise, thereby improving bitline swing. To verify the proposed techniques, a 32 kb array of the proposed 10T bit-cell is fabricated in 90 nm CMOS technology. The hardware measurement results demonstrate that this bit-cell array successfully operates down to 160 mV. For leakage power comparison, we also fabricated 49 kb arrays of the 6T and the proposed 10T bit-cells. Measurement results show that the leakage power of the proposed bit-cell is close to that of the 6T (between 0.96x and 1.22x of 6T).

A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

The paper presents an SRAM array with bit interleaving and read scheme. The SRAM test-chip is fabricated in a 90nm CMOS technology. For leakage comparison, 49 kb arrays are implemented for both the conventional 6T cell and 10T cell. The leakage power consumption of this SRAM is close to that of the 6T cell (between 0.96times and 1.1times) even though it has extra transistors in a cell. This is because the subthreshold leakage from the bitline to the cell node is drastically reduced by the stacking of devices in the leakage path. The design operates at 31.25 kHz with a 0.18 V supply. With more aggressive wordline boosting of 80 mV, the VDD scales down to 0.16 V at 0.16 V VDD, the operating frequency is 500 Hz and power consumption is 0.123 muW.

A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications

We present a voltage-scalable and process-variation resilient, hybrid memory architecture, suitable for use in MPEG-4 video processors such that power dissipation can be traded for graceful degradation in “quality.” The key innovation in our proposed work is a hybrid memory array, which is a mixture of conventional 6T and 8T SRAM bit-cells. The fundamental premise of our approach lies in the fact that the human visual system is mostly sensitive to higher order bits of luminance pixels in video data. We implemented a preferential storage policy in which the higher order luma bits are stored in robust 8T bit-cells while the lower order bits are stored in conventional 6T bit-cells. This facilitates aggressive scaling of supply voltage in memory as the important luma bits, stored in 8T bit-cells, remain relatively unaffected by voltage scaling. The not-so-important lower order luma bits, stored in 6T bit-cells, if affected, contribute insignificantly to the overall degradation in output video quality. Simulation results show that under iso-area condition, we can obtain at least 32% power savings in the hybrid memory array compared to the conventional 6T SRAM array.

Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation

Supply voltage scaling is one of the easiest ways to reduce energy dissipation. Therefore, researchers have considered subthreshold logic as a promising option to achieve ultra low energy dissipation. However, circuit propagation delay is extremely sensitive to PVT variations under subthreshold operation. Hence, large delay margin is required for successful operation of conventional synchronous designs. Since leakage energy contributes to a substantial portion of total energy dissipation in subthreshold operation, the leakage energy dissipated for the required delay margin degrades energy efficiency significantly. In addition, even small intra-die variations result in large clock skew and hence, it is difficult to efficiently handle timing issues such as the setup and the hold time violations. In this work, we explore asynchronous design approach to address these challenges in subthreshold operation. We employ critical-path replica to generate completion signals of combinational logic blocks and use classical four-phase handshaking for communication between pipeline flip-flops. Since the proposed design approach uses only local clock buffers, it is easier to handle timing problems compared to synchronous designs. We compared iso-yield minimum energy dissipation of two design approaches (synchronous and asynchronous) in an inverter chain. Despite leakage overhead due to pad delay of critical-path delay line and ?return-to-zero? time of four-phase handshaking, the proposed asynchronous design shows 71% energy savings compared to its synchronous counterpart. To demonstrate subthreshold operation of the proposed design approach, we fabricated an 8-tap FIR filter in 90 nm CMOS. Measured oscilloscope plots of handshaking and output bus signals show that the design operates successfully below 300 mV. We also measured energy consumption of the FIR filter from 19 test chips-the average was 4.64 pJ and the standard deviation was 0.3526 pJ.

Robust Level Converter for Sub-Threshold/Super-Threshold Operation:100 mV to 2.5 V

For ultra low power application, digital sub-threshold logic design has been explored. Extremely low power supply (VDD) of sub-threshold logic results in significant power reduction. However, it is difficult to convert signals from core logic to input/output (I/O) circuits since core VDD is vastly different from high I/O supply voltage. In this work, we propose a level converter based on dynamic logic style for sub-threshold I/O part, having a large dynamic range of conversion. For the level converter, high voltage clock signal needs to be delivered through separate clock path from core logic, leading to clock synchronization problem between high voltage and low voltage clocks. To overcome this issue, we employed a Clock Synchronizer. A test chip is fabricated in 130-nm CMOS technology in order to verify the proposed technique. Hardware measurement results show that the level converter successfully converts 0.3 V 8 MHz pulse to 2.5 V signal.

Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications

In low-voltage operation, static random-access memory (SRAM) bit-cells suffer from large failure probabilities with technology scaling. With the increasing failures, conventional SRAM memory is still designed without considering the importance differences found among the data stored in the SRAM bit-cells. This paper presents a heterogeneous SRAM sizing approach for the embedded memory of H.264 video processor, where the more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. As a result, the failure probabilities significantly decrease for the SRAM cells storing the more important bits, which allows us to obtain the better video quality even in lower voltage operation. In order to find the SRAM bit-cell sizes that achieve the best video quality under SRAM area constraint, we propose a heterogeneous SRAM sizing algorithm based on a dynamic programming. Compared to the brute-force search, the proposed algorithm greatly reduces the computation time needed to select the SRAM bit-cell sizes of 8 bit pixel. Experimental results show that under iso-area condition, the heterogeneous SRAM array achieves significant PSNR improvements (average 4.49 dB at 900-mV operation) compared to the conventional one with identical cell sizing.

Robust level converter design for sub-threshold logic

The large supply voltage difference between sub-threshold core logic and I/O makes it extremely challenging to convert signals from core circuit to I/O circuit. In this paper, we propose two novel circuits, clock synchronizer and reduced swing inverter to design dynamic and static level converters for sub-threshold logic. Circuit simulations shows that our level converters work at frequency > 500kHz between 20degC and 40degC with a supply voltage of 0.25V

A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors

We present a voltage-scalable and process-variation resilient memory architecture, suitable for MPEG-4 video processors such that power dissipation can be traded for graceful degradation in “quality”. The key innovation in our proposed work is a hybrid memory array, which is mixture of conventional 6T and 8T SRAM bit-cells. The fundamental premise of our approach lies in the fact that human visual system (HVS) is mostly sensitive to higher order bits of luminance pixels in video data. We implemented a preferential storage policy in which the higher order luma bits are stored in robust 8T bit-cells while the lower order bits are stored in conventional 6T bit-cells. This facilitates aggressive scaling of supply voltage in memory as the important luma bits, stored in 8T bit-cells, remain relatively unaffected by voltage scaling. The not-so-important lower order luma bits, stored in 6T bit-cells, if affected, contribute insignificantly to the overall degradation in output video quality. Simulation results show average power savings of up to 56%, in the hybrid memory array compared to the conventional 6T SRAM array implemented in 65nm CMOS. The area overhead and maximum output quality degradation (PSNR) incurred were 11.5% and 0.56 dB, respectively.

Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling

Variability in process parameters is making accurate estimate of nano-scale SRAM stability an extremely challenging task. In this paper, we propose a new method to detect the read failure in an SRAM cell using critical point sampling technique. Using this technique, we propose two types of read failure probability estimation method, (1) quasi-analytical and (2) completely analytical method. The result shows that our proposed model can achieve high accuracy, while being 20/spl times/ faster in computational speed. Our method can be applied to different phases of design to reduce the overall design time, and can be used for optimizing the given design in order to obtain a better yield.

A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18

We present a 2-Kb one-time programmable (OTP) memory for UHF RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Reliability of memory cell is enhanced by limiting the maximum terminal voltages of thin-oxide and thick-oxide transistors to 1.8 V and 3.3 V, respectively. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. To further reduce power consumption, we develop a novel power-efficient charge pump. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 m 1-poly 6-metal standard CMOS process with no additional masks. The total area of the chip including the I/Os and bonding pads is 2.3 × 1.5 mm2 where the OTP memory area is only 0.43 × 0.31 mm2. Our tag IC measurement shows that the read and write currents of the OTP memory are 17 μA and 58 μA, respectively.