Jinsang Kim

Multiple feature clustering for image sequence segmentation

Abstract We present a segmentation scheme in order to develop a method which can identify homogeneous regions to represent higher level objects for content-based functionality. The proposed scheme extracts multiple features, such as motion and texture, on the pixel basis. Different weights are applied to each feature components based on motion confidence measures. The proposed scheme consists of two phases. In the first phase, a multiple feature space is transformed to one-dimensional label space using a self-organizing feature maps (SOFM) neural network clustering method. In the second phase, the neural network outputs are merged in order to generate desired segmentation resolution. Our experimental results and performance analysis show the validity of the proposed scheme.

Supply Voltage Decision Methodology to Minimize SRAM Standby Power Under Radiation Environment

In static random access memory, standby power is the summation of scrubbing and leakage powers. In terrestrial environments, the leakage power is more dominant than the scrubbing power. Hence, the conventional methodology to reduce SRAM standby power is to lower VDD to possible minimum voltage under process, voltage, and temperature variations. However, under severe radiation environments such as space, high scrubbing rate is indispensable to prevent the accumulation of soft-errors, making the scrubbing power have a substantial portion of total standby power. Since the soft-error rate becomes higher with the VDD scaling, the conventional methodology may not be valid under radiation environments. We present a methodology to decide optimal supply voltage with respect to standby power under radiation. We visualize our methodology under solar max/min galactic cosmic ray radiation environment of geosynchronous earth orbit and three error correction code (ECC) scenarios: Hamming code, double-error-correction (DEC) Bose-Chaudhuri-Hocquenghem (BCH) code, and triple-error-correction (TEC) BCH code. In 65 nm CMOS, Hamming code fails to deliver our target decoded bit-error-rate. Under other ECCs, the proposed methodology shows that 0.97 V (for DEC BCH) and 0.8 V (for TEC BCH) are optimal. Here, we can obtain 30% (for DEC BCH) and 60% (for TEC BCH) standby power savings compared to nominal voltage (= 1.2 V), respectively.

Low-complexity fusion of intensity, motion, texture, and edge for image sequence segmentation: a neural network approach

We develop an image sequence segmentation scheme which uses intensity, motion, edge, and texture features. The proposed scheme is simple and inherently parallel in nature. Motion confidence values are employed for a feature weighting scheme in order to suppress unreliable feature components. These feature vectors are quantized by training self-organizing feature maps (SOFM). In order to generate more meaningful boundaries of the segmentation, we also develop an edge fusion algorithm in which an edge-linked map extracted from a real-time edge linking algorithm is incorporated for the segmentation. Experimental results show the validity of our approach.

Studying the Variation Effects of Radiation Hardened Quatro SRAM Bit-Cell

Quatro is one of promising SRAM bit-cells for severe radiation environment such as space. However, our study shows that under process and temperature variations of 65nm CMOS, Quatro suffers from high write failure probability, impeding the application of this SRAM bit-cell. We explore the possibility of several popular techniques, such as boosted word-line voltage and negative or boosted bit-line biasing, to improve the write stability of Quatro. We observe that this SRAM bit-cell has different write mechanism from that of the 6T SRAM. Hence, the negative bit-line biasing does not make significant achievement, unlike the 6T SRAM. In this work, we employ the boosting of both word-line and bit-line. By applying 100 mV raised voltage, we obtain robust write operations up to 250 MHz frequency.

High Performance and Hardware Efficient Multiview Video Coding Frame Scheduling Algorithms and Architectures

Multiview video coding (MVC) provides more realistic 3-D scenes adding depth information derived from multiple cameras than single-or stereo-view video coding. In MVC, video frames obtained from each view are simply scheduled to corresponding encoding channels. However, under such a conventional scheduling technique the encoding times of each channel may not be identical, degrading encoding performance. To address this problem, this paper proposes two MVC frame scheduling schemes and their architectures: a hardware resource aware scheduling and a frame waiting time aware scheduling (WTaS). Here, WTaS considers the waiting time of each frame stored in on-chip SRAM during frame scheduling, thereby reducing SRAM size significantly. Experimental results show that the proposed frame scheduling schemes provide 29.4% faster processing time, compared to the conventional counterpart. In addition, we can improve the core area, on-chip SRAM area, and the power dissipation by 26.7%, 23.2%, and 26.6%, respectively.

Segmentation of image sequences using SOFM networks

We present a segmentation technique for image sequences using self organizing feature maps (SOFM). Our goal is to develop a method which can identify homogeneous regions in a frame to represent higher level objects for content based manipulation of image sequences. The proposed scheme extracts pixel based multiple features, such as motion and textures, and then, different weights are applied to each feature component based on motion confidence measures. These multiple feature spaces are transformed to one dimensional label space by using the SOFM. The oversegmentation neural network outputs are merged in order to generate desired segmentation resolution. Our experimental results show the validity of the proposed scheme.

a-SAD: power efficient SAD calculator for real time H.264 video encoder using MSB-approximation technique

We propose a power efficient SAD calculator, namely a-SAD. We use MSB-approximation where some highest-order MSBs are approximated to single MSB. Our theoretical analysis shows that this technique simultaneously improves performance and power of SAD circuit. We obtain optimal number of approximated MSBs from video experiments, which is the largest number not to affect video compression rate. In our simulations, our a-SAD circuit delivers higher performance compared to previous SAD circuits. We compare power dissipation under iso-performance scenario, where our a-SAD circuit shows 27% power saving compared to a previous design.

Low complexity image correction using color and focus matching for stereo video coding

In three-dimensional video (3DV), two cameras capture the same scene from different viewpoints. Color and focus variations between the camera views may deteriorate the 3DV quality and performance of 3DV coding. Therefore, we need to correct the color and focus discrepancy between the camera views. In this paper, we propose algorithms that color and focus correction are combined in a preprocessing step of the stereo video coding. For both color and focus matching, we calculate only disparity vector (DV) once during disparity estimation (DE), since the proposed color and focus correction algorithm can share the disparity vector. The experimental results show that the proposed color and focus correction algorithm provides better image quality and coding performance.

A VLSI architecture for image sequence segmentation using edge fusion

We propose a segmentation scheme and its VLSI edge fusion architecture for image sequences which provides initial region information for the semantic object representation of image sequences. The proposed scheme incorporates static and dynamic features simultaneously in one scheme. The segmentation results of both gray level image sequences and color image sequences are evaluated using a evaluation metric. Also, based on complexity analysis of the segmentation scheme, the edge fusion is the bottleneck of fast image sequence segmentation. The proposed VLSI architecture makes it possible to the image sequence segmentation in real-time.

Low power block matching using pattern based pixel truncation

A power efficient block matching algorithm is proposed using pattern based pixel truncation scheme. Our observation shows that during block matching, if we represent the block matching process as a one-dimensional signal, we can see clearly that the signal has repeated mountain- and valley-like regions. Utilizing this feature, the proposed low power block matching scheme truncates pixels except the pixels of the valley-like SAD values, which have high chance to be the minimum SAD value. We synthesized the proposed algorithm to measure the switching power dissipation. The results show that the proposed BMA architecture obtains at least 76% power saving with negligible coding performances.