Minsu Choi

Optimal spare utilization in repairable and reliable memory cores

Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies the largest portion of the SoC area; this trend much likely will continue in the future as it is widely anticipated that it will approach the 94% level by the year 2014. As memory cells are more prone to defects and faults than logic cells, redundancy has been extensively used for enhancing defect and fault tolerance through repair by spare (row and column) replacement. Unlike legacy PCB (printed circuit board) or MCM (multichip module) based systems, embedded cores cannot be physically replaced once they are fabricated onto a SoC. To realize both enhanced manufacturing yield and field reliability, ATE (automated test equipment) and BISR (built-in-self-repair) are utilized to allocate redundancy for the embedded memory cores. As ATEs (for the repair of manufacturing defects) and BISR (for repairing field faults) rely on the provided redundancy (rows and columns), spare partition and utilization techniques are proposed in this paper to achieve an optimal combination of yield and reliability for embedded memory cores. Parametric simulation results for the single dimensional (i. e., spare columns) and two-dimensional (i. e., both spare columns and rows) cases are provided.

Cost-driven optimization of fault coverage in combined Built-In Self-Test/Automated Test Equipment testing

As the design and fabrication complexities for the instrumentation-on-silicon systems intensify, optimization of combined Built-In Self-Test (BIST) and Automated Test Equipment (ATE) testing becomes more desirable to meet the required fault-coverage while maintaining acceptable cost overhead. The cost associated with combined BIST/ATE testing of such systems mainly consists of the following; (1) the cost induced by the BIST area overhead and (2) the cost induced by the overall testing time. In general, BIST has faster testing speed than ATE, while it can provide only limited fault-coverage and driving higher fault-coverage from BIST means additional area cost overhead. On the other hand, higher fault-coverage can be usually achieved from ATE, but excessive use of ATE results in additional test time cost. Fault-coverage of BIST and ATE plays a significant role since it can affect the area overhead in BIST and test time in BIST/ATE. This paper is to propose a novel numerical method to find an optimized fault-coverage implemented in BIST and ATE so that a minimum cost can be achieved. The proposed method. then, is applied to two parallel combined BIST/ATE testing schemes to assure its technical validity.

A novel technique to minimize standby leakage power in nanoscale CMOS VLSI

This paper proposes a novel approach to minimize leakage currents in CMOS circuits during the off-state (or standby mode, sleep mode) by applying the optimal reverse body bias to the substrate (body or bulk) to increase the threshold voltage of transistors. The optimal bias point is determined by comparing the sub-threshold current (ISUB) and band-to-band current (IBTBT) simultaneously. The proposed circuit was simulated in HSPICE using 32 nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperature (ranging from 25°C to 100°C). Analysis of the results shows a maximum of 551 and 1491 times leakage power reduction at 25°C and 100°C on a circuit with 546 gates. The proposed approach demonstrates that the optimal body bias reduces considerable amount of the leakage power in the nanoscale CMOS integrated circuits. In this approach, the temperature and supply voltage variations are compensated by the proposed feedback loop.

Modeling yield of carbon-nanotube/silicon-nanowire FET-based nanoarray architecture with h-hot addressing scheme

With molecular-scale materials, devices and fabrication techniques recently being developed, high-density computing systems in the nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs) and silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered one of the most significant challenges. In this paper we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used (1) to accurately estimate the raw and net array densities, and (2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture. As a case study, the proposed yield model is applied to the defect-tolerant addressing scheme called h-hot addressing and simulation results are discussed.

Balanced redundancy utilization in embedded memory cores for dependable systems

Advances in revolutionary system-on-chip (SoC) technology mainly depend on the high performance and ultra dependable system core components. Among those core components, embedded memory system core, currently acquiring 54% of SoC area share, will continue its domination of SoC area share as it is anticipated to approach about 94% of SoC area share by the year 2014. Since memory cells are considered as more prone to defects and faults than logic cells, redundancy and repair have been extensively practiced for enhancing defect and fault tolerance. Unlike in legacy PCB (printed circuit board) or MCM (multichip module) based systems, embedded core components cannot be physically replaced once they are fabricated onto a SoC. To realize enhanced manufacturing yield and field reliability, both ATE (automated test equipment) and BISR (built-in-self-repair) are commonly utilized to allocate redundancy for embedded memory system cores. Since ATE (for repairing manufacturing defects) and BISR (for repairing field faults) share the given redundancy, balanced redundancy partitioning and utilization techniques are proposed in this paper to achieve optimal combination of yield and reliability of the embedded memory system core. Parametric simulation results for both single dimensional (i.e., spare columns) and two dimensional (i.e., both spare columns and rows) are shown.

Teaching nanotechnology by introducing crossbar-based architecture and quantum-dot cellular automata

The end of photolithography as the driver for Moores law is predicted within seven to twelve years and six different emerging technologies (mostly nanoscale) are expected to replace the current CMOS-based system integration paradigm. As nanotechnology is emerging, (1) there is a strong need for well-educated nanoscale systems engineers by industry, and (2) research and education efforts are also called to overcome numerous nanoscale systems issues. This paper is to propose a way to teach nanotechnology by introducing two emerging technologies: crossbar-based nanoarchitecture and quantum-dot cellular automata.

Reliability measurement of mass storage system for onboard instrumentation

Advances in spaceborne vehicular technology have made possible the long-life duration of the mission in harsh cosmic environments. Reliability and data integrity are the commonly emphasized requirements of spaceborne solid-state mass storage systems, because faults due to the harsh cosmic environments, such as extreme radiation, can be experienced throughout the mission. Acceptable dependability for these instruments has been achieved by using redundancy and repair. Reconfiguration (repair) of memory arrays using spare memory lines is the most common technique for reliability enhancement of memories with faults. Faulty cells in memory arrays are known to show spatial locality. This physical phenomenon is referred to as fault clustering . This paper initially investigates a quadrat-based fault model for memory arrays under clustered faults to establish a reliable foundation of measurement. Then, lifelong dependability of a fault-tolerant spaceborne memory system with hierarchical active redundancy, which consists of spare columns in each memory module and redundant memory modules, is measured in terms of the reliability (i.e., the conditional probability that the system performs correctly throughout the mission) and mean-time-to-failure (i.e., the expected time that a system will operate before it fails). Finally, minimal column redundancy search technique for the fault-tolerant memory system is proposed and verified through a series of parametric simulations. Thereby, design and fabrication of cost-effective and highly reliable fault-tolerant onboard mass storage system can be realized for dependable instrumentation.

Quality enhancement of reconfigurable multichip module systems by redundancy utilization

This paper evaluates the quality effectiveness of redundancy utilization in reconfigurable multichip mode (RMCM) systems. Due to reconfigurability, the RMCM system can implement a device with different redundancy levels. A redundancy level is determined by the requirement of fault tolerance (FT) of the device under implementation which can be realized through reconfiguration. No previous work has adequately investigated the effect of utilization of redundancy on the quality-level (QL) of RMCM. In this paper, the tolerance to escape from testing is also introduced to provide more extensive and comprehensive analysis and is referred to as escape tolerance (ET). This can be achieved by utilizing an appropriate amount of redundancy and is exploited for evaluating its effect on the QL of RMCM with different utilizations of redundancy. It is shown through theoretical analysis that the coverage of testing [i.e., fault coverage (FC)] can be improved by reconfiguration. Thus, we derive the QL by relating the QL to the yield enhancement by reconfiguration, the effect of interconnection yield and ET on the QL, and the improvement in FC by reconfiguration. In the proposed approaches, appropriate combinatorial models are formulated to take into account the parameters related to the redundancy and reconfiguration process in RMCM systems. From the extensive parametric simulation results, it is shown that there exists a bound in the effectiveness of redundancy utilization (i.e., the amount of redundancy) depending on the RMCM yield and FC. Using the proposed approach, the redundancy utilization in RMCM systems can be appropriately used to enhance the QL.

Spare Line Borrowing Technique for Distributed Memory Cores in SoC

In this paper, a new architecture of distributed embedded memory cores for SoC is proposed and an effective memory repair method by using the proposed spare line borrowing (software-driven reconfiguration) technique is investigated. It is known that faulty cells in memory core show spatial locality, also known as fault clustering. This physical phenomenon tends to occur more often as deep submicron technology advances due to defects that span multiple circuit elements and sophisticated circuit design. The combination of new architecture & repair method proposed in this paper ensures fault tolerance enhancement in SoC, especially in case of fault clustering. This fault tolerance enhancement is obtained through optimal redundancy utilization: spare redundancy in a fault-resistant memory core is used to fix the fault in a fault-prone memory core. The effect of spare line borrowing technique on the reliability of distributed memory cores is analyzed through modeling and extensive parametric simulation

Need for undergraduate and graduate-level education in testing of microelectronic circuits and systems

As deep-sub-micron and beyond technology emerges, quality assurance of microelectronic circuits and systems becomes more important than ever. Consequentially, (1) a strong need for well-educated microelectronic circuits and systems test engineers is desired by the industry, (2) graduate-level research efforts are also called to overcome numerous microelectronic circuits and systems test issues. This paper is to address issues related to increasing impact of the electronic circuits and systems test field on education in electrical and computer engineering and to propose suitable educational topics for undergraduate and graduate-level electrical and computer engineering courses.