Ik-Soo Eo

Physical design methodology of power gating circuits for standard-cell-based design

The application of power gating circuits to semicustom design based on standard-cell elements is limited due to the requirement of customizing cells that are tailored for power gating or the requirement of customizing physical design methodologies for placement and power network. We propose a new power network architecture that enables use of conventional standard-cell elements. A few custom library elements are developed wherever needed, including output interface circuits and data retention storage elements. A novel method of current switch design is also described. The proposed methodology is applied to ISCAS benchmark circuits, and also to a commercial Viterbi decoder with 0.18mum CMOS technology

Performance Analysis Of A Dsttd System With Decision-Feedback Detection

We investigate closed-form bit error rate (BER) expressions for the double space-time transmit diversity (DSTTD) system with a zero-forcing decision-feedback (ZF-DF) detector. We show that the lower Alamoutis STTD unit can obtain the second order diversity gain. However, the upper one cannot guarantee the fourth order diversity due to the effect of error propagation. For example, it simply gives 3.5 dB signal-to-noise ratio (SNR) advantage over the lower one at the bit error rate (BER) of 10-3. Under the same environment, overall BER performance also suffers from 5.6 dB performance degradation over a maximum likelihood (ML) detector

Reliable blind channel estimation scheme based on cross-correlated cyclic prefix for OFDM system

This paper proposes an efficient and reliable blind channel estimation method for single transmitter and receiver antenna orthogonal frequency division multiplexing (OFDM) system. The proposed blind channel estimation method is based on the interesting cross-correlation property of the repeated structure of cyclic prefix (CP) in an OFDM symbol. Our cross-correlation based method, which utilizes the only information in CP, not entire symbol, is robust to additive white noise and not affected from the presence of null channel coefficients. Toeplitz structure induced in the cross-correlation matrix allows us a simple and reliable method for extracting channel impulse response effectively. In the simulation study, proposed method is compared with auto-correlation based approach and it demonstrate the superior performance of the proposed method

Blind Channel Estimation and Equalization in OFDM System With Circular Precoding

This paper proposes a reliable and efficient blind channel estimation method and a linearly constrained minimum variance (LCMV) receiver with circular precoding for single transmitter and receiver antenna orthogonal frequency division multiplexing (OFDM) system. The proposed blind channel estimation method is based on the interesting cross-correlation property of the cyclic prefix (CP) in an OFDM symbol. Toeplitz structure induced in the cross-correlation matrix allows us to employ a simple and reliable method for extracting channel impulse response effectively. The LCMV optimization criterion is applied for symbol detection of the OFDM symbols. At the same time, a circular precoding scheme for minimizing the maximal power of the dominant interference plus noise in LCMV receiver is considered. In the simulation study, proposed method is compared with other circularly precoded scheme and it demonstrate the superior performance of the proposed method

High speed code acquisition for wideband CDMA system

In CDMA (code division multiple access) system the first action for exchanging information is code acquisition which is finding spreading code position. Thus the high-speed code acquisition is very important technology for successful communication. We propose parallel code acquisition system, the code acquisition time is reduced by the parallel structure. But the parallel code acquisition structure needs so many gates that are increasing the chip area and power consumption, thus we propose the parallel code acquisition hardware with small gate design. The efficient design is achieved with function sharing and structure. The designed 16 parallel code acquisition is about 32000 gates compared with 8000 gates of one parallel code acquisition.

WLL base station modem ASIC

WLL (wireless local loop) concerns the transmission of information without wire connection. This supplies voice, fax, and data services. The wireless communication system has the advantages of small construction time and high data rate service. For the air interface specification satisfaction we need a base station and terminal station. We design the base station modem, which is supports the Korean standard WLL system specification. The functions of the modem are forward modulation, reverse demodulation and deinterleaver and Viterbi decoder. We started with VHDL coding, carried out verification and synthesized the coding. The designed chip has 106000 gates and 7 kbits static RAM by 0.5 /spl mu/m CMOS standard cell technology.