Kyung-Jin Byun

A fast ACELP codebook search method

The ACELP coding algorithm has been widely adopted in standard speech coders due to the advantages of codebook storage and the efficient search scheme. Especially, the focused search and the depth first tree search are very efficient methods dramatically reducing the search complexity while providing a good sub optimal solution. In this paper, we propose a fast algebraic codebook search method which improves the depth first tree search method: The proposed method reduces the search complexity by pruning the trees which are less possible to be selected as an optimum excitation. This method needs no additional computation for the selection of trees to be pruned and reduces the computational complexity considerably compared with the original depth first tree search method with very slight degradation of speech quality. We also implemented a GSM EFR codec chosen as an example to examine our method on the 16 bit fixed-point DSP.

Method for processing speech signal in speech processing system

A method for processing an input speech signal to be applied to a CELP vocoder has the steps of obtaining preliminary pitch search intervals by a preprocessing autocorrelation expression from a pitch lag of a synthesized speech signal which is synthesized from a residual signal of the input speech signal; computing coefficients of pitch filter with respect to the preliminary pitches; searching a high interval in the autocorrelation; and removing the remaining interval other than the high interval in the pitch lag. Since the present invention proposes a speech processing method which uses only a high interval in autocorrelation of a voice waveform in pitch-searching, and where such a speech processing method is embodied in a CELP vocoder, total computation time of the CELP vocoder can be decreased 37% or more without lowering speech quality. Therefore, a digital signal processor, which is low in price and is slow in speed, can be embodied in a CELP vocoder.

Real-time Implementation of AMR and AMR-WB using the Fixed-point DSP for WCDMA Systems

This paper presents an implementation of the AMR and AMR-WB speech codecs using the fixed-point TeakLite DSP for the WCDMA mobile station. Since the AMR and AMR-WB are based on the ACELP coding algorithm and the ACELP requires huge complexity in the codebook search, we especially focused on the optimization of the codebook search routine in our implementations. The implemented AMR and AMR-WB codecs require only 24 MIPS of computation at 12.2 kbps mode and 52.2 MIPS at 23.85 kbit/s mode, respectively by exploiting the DSP architecture and managing the memory structure efficiently. The implemented AMR and AMR-WB codecs were verified through passing all the test vectors provided by 3GPP with maintaining the bit-exactness, and stable operation on the real-time testing board was also confirmed. In addition, to reduce further complexity we propose a fast search method, which improves conventional depth-first tree search method generally utilized in ACELP coding algorithm

Computationally efficient implementation of AMR speech coder

The adaptive multi-rate speech codec consists of eight source codecs with bit rates from 4.75 to 12.2 kbit/s. This paper presents an AMR implementation especially focused on reducing the computational complexity. In order to reduce the computational load, we propose the fast codebook search method that is simply modified version of the depth first tree search method used in algebraic codebook search in the AMR codec. For the AMR implementation we designed the 16 bit fixed-point DSP based on the TeakLite DSP core, which was tailored for the AMR implementation. The implemented AMR codec requires only 19.6 MIPS of computation for the highest complexity mode of the AMR by using the fast search method and exploiting the DSP architecture and managing the memory structure efficiently. It is verified with all the test vectors provided by 3GPP, and stable operation on the real-time testing board was also confirmed.

Implementation of 13 kbps QCELP vocoder ASIC

In this paper an efficient implementation of a 13 kbps QCELP vocoder ASIC having a speech compression function used in the digital mobile communication is presented The 13 kbps QCELP algorithm has better quality than 8 kbps one, but it requires much more computation. Especially, the complexity load of the pitch and codebook search process for speech synthesis is predominant. We propose an optimized routine for convolution computation by utilizing pipeline structure characteristics of the DSP. Our DSP, specifically designed for vocoder applications, is a 16-bit fixed-point one. We adopt RISC type instruction set, distributed decoding, alternative program fetch, dual bank memory structure, and repeat loop without loss in order to reduce the power consumption and to obtain fast operating capability while keeping the chip size small. The concurrent development of the DSP and the QCELP assembly code enables us to optimize the assembly code more successfully than adopting other general-purpose DSP chips.

On FHD 300MHz@60fps, intra/inter CU mode decision hardware architecture for the Hypernova H.265 encoder

H.265 (HEVC) is the latest joint video coding standard with ITU-T SG16 WP and ISO/IEC JTC1/SC29/WG11. Its coding efficiency is about two times compared to H.264. However the burden of coding unit (CU) mode decision with rate distortion optimization (RDO) is too costly to implement it with hardware. The key idea of this paper is a novel mode decision architecture to reduce the HW complexity of RDO that is the most effective on an encoders performance without a noticeable PSNR loss. To shrink the size the Hypernova H.265 encoder uses simplified RDO blocks and shares the transform resources. Its operating clock frequency is 300MHz@60fps on FHD image and BD-BR increase is negligible at 6.02% on hardware aspect. The estimated gate count of its is around 1M.

Multi-core architecture for video decoding

Multiple international video standards in the market have been developed successfully for many commercial products. This paper proposes a new multimedia core and multi-core architecture for multi-standard video decoding. The proposed multimedia core is based on the 6-stage pipelined dual issue VLIW+SIMD architecture and efficient instructions for video decoding. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. The multi-core architecture consisting of eight multimedia cores is efficient for parallel decoding of various video compression formats including MPEG-2, MPEG-4, AVS and H.264/AVC.

Performance improvement of double-talk detection algorithm in the acoustic echo canceller

This paper deals with a delay problem in the endpoint detection of the double-talk detection algorithm in the acoustic echo canceller. In the case that past power is much larger than current power such as at the end of a double-talking period, the power estimated using the forgetting factor decreases slowly to cause the delay problem in the endpoint detection. Two methods are proposed to solve this problem. One is replacing the current power periodically by a new average power, and the other is removing the past power term in a recursive equation or replacing it by other values. The simulation results show that proposed methods outperform the conventional method in the endpoint detection of double-talking periods without. increasing the computational burden much.

Multi-core based HEVC hardware decoding system

In this demo, a scalable HEVC hardware decoder is demonstrated for various applications including UHD. The architecture includes a control logic for multi-core management and flexible in-loop filters that can process boundaries of picture partitions without a separate in-loop filter unit from the pipeline. Two-level parallel processing approach makes the decoder operate in real-time for high-performance applications. The demonstration on FPGA prototype board shows the efficiency of the proposed scalable architecture achieved by multi-core design. The system is estimated to be able to decode UHD video coded by HEVC in real-time.

Development of portable sound effector

This paper presents an implementation of portable sound effector using the tiny packaged sound effect module which includes implemented sound effects, sound effect SoC, and EEPROM. The SoC integrates the embedded DSP core, an audio codec, some peripheral blocks, and various sound effect algorithms where cost savings made by reducing the chip count and size. In the implementation of sound effect algorithms, we employ the primitive functions of the DSP compiler, which provide an efficient way to optimize the compiled code. This portable sound effector is developed as an all-in-one product for the low cost and high portability.