Ilan Y. Spillinger

Performance evaluation of a decoded instruction cache for variable instruction-length computers

A Decoded INstruction Cache (DINC) serves as a buffer between the instruction decoder and the other instruction-pipeline stages. In this paper we explain how techniques that reduce the branch penalty based on such a cache, can improve CPU performance. We analyze the impact of some of the design parameters of DINCs on variable instruction-length computers, e.g., CISC machines. Our study indicates that tuning the mapping function of the instructions into the cache, can improve the performance substantially. This tuning must be based on the instruction length distribution for a specific architecture. In addition, the associativity degree has a greater effect on the DINCs performance, than on the performance of regular caches. We also discuss the difference between the performance of DINCs and other caches, when longer cache lines are used. The results presented were obtained by both analytical study and trace-driven simulations of several integer UNIX applications.

Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine

This work deals with some performance aspects of the implementation of an algorithm to simulate MOS electronic circuits, modeled at the transistor level. The target architecture is a special purpose logic simulation machine, the Yorktown Simulation Engine (YSE), which has no direct support for loop mechanisms or conditional flow control. Since the simulation algorithm requires such mechanisms to determine whether and when a circuit reaches a steady state, we must calculate prior to simulation time, the number of iterations required for the algorithm to converge. We show how to arrange the order in which transistors are processed, aiming at a reduced number of such iterations, and therefore, an improved simulation performance. The results presented here show the optimal way to deal with acyclic circuits and some heuristic criteria to handle cyclic circuits. Also, we show a method to calculate the number of iterations required for the convergence of the simulation algorithm. These methods, originally developed for the YSE, have been also incorporated in a switch level simulator running on an IBM/370 architecture.

Whistle: a workbench for test development of library-based designs

The authors have applied the difference fault model (DFM) approach to the simulation of high-level designs and built a complete environment for test generation and fault simulation of designs expressed in a hardware description language (HDL), such as VHDL. Their environment, called Whistle, consists of a set of programs that supports a library-based design style. They describe the tools in Whistle, with special emphasis on the tools used to analyze each block in the design library, and the generation of code for the simulation of the F-faults in the design. The authors then evaluate Whistle from several points of view. First, they illustrate the accuracy of the fault coverage estimates by comparing them with the actual fault coverage obtained by gate-level fault simulation. Second, they examine the correlation between the accuracy measurements as given by their evaluation functions and the behavior of various characterization functions for a given block. This illustrates how critical it is to choose a good characterization function and how it affects the accuracy of the results. A third aspect of Whistle that they look at is its test-generation capability.<<ETX>>

Functional fault simulation as a guide for biased-random test pattern generation

An approach to the generation of test patterns for implementation-level faults is presented. The approach involves fault simulation on a functional-level description of a combinational VLSI design, together with an appropriate functional fault model. The methodology uses the difference fault model (DFM), a formal abstraction of the faults at the implementation level, as the basis for fault simulation at the functional level. Incremental information from fault simulation results provides guidance for the generation of nonuniformly random test patterns using a backtracing process. The quality of the generated patterns is measured in terms of their coverage of implementation faults. >

Using functional fault simulation and the difference fault model to estimate implementation fault coverage

An approach to estimate the fault coverage of the implementation of a VLSI design obtained by fault simulation at the function level is presented. The proposed methodology begins by defining a fault model for the functional level, the difference fault model (DFM), which reflects all of the faults in the implementation level. Functional fault detection is recorded by performing a functional simulation of the design, with faults injected as determined by the DFM. The last step is to use the correspondence between the functional faults (in the DFM) and those of the implementation level to yield an estimate of the implementation fault coverage. The results obtained show a very good correlation between the estimated fault coverage, based on fault simulation at the functional level, and the actual fault coverage obtained by fault simulation on a gate-level implementation. >

G-RIDDLE: a formal analysis of logic designs conducive to the acceleration of backtracing

A formal approach to the analysis of combinatorial gate-level designs is presented which produces information conducive to the acceleration of test generation algorithms. This analysis yields, as its main product, information which can be used to reduce the amount of effort expended during backtracing by guiding this process towards decision (assignments) less likely to cause conflicts and by minimizing the amount of work between backtracks. The G-RIDDLE approach is introduced for performing this analysis, as a refinement of the more general case which handles designs consisting of multi-input/multioutput combinatorial blocks. Experimental results are given for a popular benchmark of combinatorial gate-level designs.<<ETX>>

Performance evaluation of a decoded instruction cache for variable instruction length computers

A Decoded INstruction Cache (DINC) is a buffer between the instruction decoder and other instruction pipeline stages. In this paper, we explain how techniques that reduce the branch penalty on a DINC, can improve CPU performance. We also analyze the impact of some of the design parameters of DINCs on variable instruction length computers. Our study indicates that tuning the mapping of the instructions into the cache can improve performance substantially. Tuning must be based on the instruction length distribution for a specific architecture. In addition, the associativity degree has a greater effect on the DINCs performance than on the performance of regular caches. We discuss the difference between the performance of DINCs and other caches, when longer cache lines are used. We present a model to estimate the miss rate based on its characteristics, that are discussed and analyzed throughout this paper. Our conclusions are based on both analytical study and trace driven simulations of several integer UNIX applications. >

RIDDLE: a foundation for test generation on a high level design description

A formal approach is presented to the analysis of a VLSI design described at the high level, which produces information conducive to the acceleration of test-generation algorithms. This analysis yields information which can be used to reduce the amount of effort expended during backtracking, by guiding this process towards decisions (assignments) less likely to cause conflicts and minimizing the amount of work between backtracks. RIDDLE, an algorithm that performs this analysis in time that is linear in the number of signals, is introduced. Experimental results for the special case of combinatorial gate-level designs are also given.<<ETX>>

RIDDLE: a foundation for test generation on a high-level design description

A formal approach to the analysis of a combinational circuit described at the high level is presented. It produces information conducive to the acceleration of test generation algorithms. This analysis yields, as its main product, information which can be used to reduce the amount of effort expended during backtracing, by guiding this process towards decisions (assignments) less likely to cause conflicts and minimizing the amount of work between backtracks. RIDDLE, an algorithm which performs this analysis in time linear in the number of signals, is introduced. Experimental results for the special case of combinational gate-level designs are also given. >