Ilgweon Kang

Incremental multiple-scan chain ordering for ECO flip-flop insertion

Testability of ECO logic is currently a significant bottleneck in the SOC implementation flow. Front-end designers sometimes require large functional ECOs close to scheduled tapeout dates or for later design revisions. To avoid loss of test coverage, ECO flip-flops must be added into existing scan chains with minimal increase to test time and minimal impact on existing routing and timing slack. We address a new Incremental Multiple-Scan Chain Ordering problem formulation to automate the tedious and time-consuming process of scan stitching for large functional ECOs. We present a heuristic with clustering, incremental clustering and ordering steps to minimize the maximum chain length (test time), routing congestion, and disturbance to existing scan chains. Test times for our incremental scan chain solutions are reduced by 5.3%, and incremental wirelength costs are reduced by 45.71%, compared to manually-solved industrial testcases.

An algorithmic framework for efficient large-scale circuit simulation using exponential integrators

We propose an efficient algorithmic framework for time-domain circuit simulation using exponential integrators. This work addresses several critical issues exposed by previous matrix exponential based circuit simulation research, and makes it capable of simulating stiff nonlinear circuit system at a large scale. In this framework, the systems nonlinearity is treated with exponential Rosenbrock-Euler formulation. The matrix exponential and vector product is computed using invert Krylov subspace method. Our proposed method has several distinguished advantages over conventional formulations (e.g., the well-known backward Euler with Newton-Raphson method). The matrix factorization is performed only for the conductance/resistance matrix G, without being performed for the combinations of the capacitance/inductance matrix C and matrix G, which are used in traditional implicit formulations. Furthermore, due to the explicit nature of our formulation, we do not need to repeat LU decompositions when adjusting the length of time steps for error controls. Our algorithm is better suited to solving tightly coupled post-layout circuits in the pursuit for full-chip simulation. Our experimental results validate the advantages of our framework.

Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks

We design an algorithmic framework using matrix exponentials for time-domain simulation of power delivery network (PDN). Our framework can reuse factorized matrices to simulate the large-scale linear PDN system with variable stepsizes. In contrast, current conventional PDN simulation solvers have to use fixed step-size approach in order to reuse factorized matrices generated by the expensive matrix decomposition. Based on the proposed exponential integration framework, we design a PDN solver R-MATEX with the flexible time-stepping capability. The key operation of matrix exponential and vector product is computed by the rational Krylov subspace method. To further improve the runtime, we also propose a distributed computing framework DR-MATEX. DR-MATEX reduces Krylov subspace generations caused by frequent breakpoints from a large number of current sources during simulation. By virtue of the superposition property of linear system and scaling invariance property of Krylov subspace, DR-MATEX can divide the whole simulation task into subtasks based on the alignments of breakpoints among those sources. The subtasks are processed in parallel at different computing nodes without any communication during the computation of transient simulation. The final result is obtained by summing up the partial results among all the computing nodes after they finish the assigned subtasks. Therefore, our computation model belongs to the category known as embarrassingly parallel model. Experimental results show R-MATEX and DR-MATEX can achieve up to around 14.4× and 98.0× runtime speedups over traditional trapezoidal integration-based solver with fixed time-step approach.

Dynamic analysis of power delivery network with nonlinear components using matrix exponential method

In this work, we propose a matrix exponential-based time-integration algorithm for dynamic analysis of power delivery network (PDN) with nonlinear components. The presented method is an explicit method and is very competitive for applications compared to traditional low order approximation methods, such as backward Euler method with Newton-Raphson iterations (BE). The proposed method takes comparable number of time steps to complete the whole simulation. Second, the method takes only one LU decomposition per time step while BE requires at least two LU decompositions for the convergence check of solutions of nonlnear system. Moreover, our method does not need to repeat expensive LU decomposition operations when the length of time steps are adjusted for error controls. The experimental results validate our methods efficiency. We observe the reductions of total LU operation number and the simulation runtime.

ePlace-3D: Electrostatics based Placement for 3D-ICs

We propose a flat, analytic, mixed-size placement algorithm ePlace-3D for three-dimension integrated circuits (3D-ICs) using nonlinear optimization. Our contributions are (1) electrostatics based 3D density function with globally uniform smoothness (2) 3D numerical solution with improved spectral formulation (3) 3D nonlinear pre-conditioner for convergence acceleration (4) interleaved 2D-3D placement for efficiency enhancement. Our placer outperforms the leading work mPL6-3D and NTUplace3-3D with 6.44% and 37.15% shorter wirelength, 9.11% and 10.27% fewer 3D vertical interconnects (VI) on average of IBM-PLACE circuits. Validation on the large-scale modern mixed-size (MMS) 3D circuits shows high performance and scalability.

Tree Structures and Algorithms for Physical Design

Tree structures and algorithms provide a fundamental and powerful data abstraction and methods for computer science and operations research. In particular, they enable significant advancement of IC physical design techniques and design optimization. For the last half century, Prof. T. C. Hu has areas in computer science, including network flows, integer programming, shortest paths, binary trees, global routing, etc. In this article, we select and summarize three important and interesting tree-related topics (ancestor trees, column generation, and alphabetical trees) in the highlights of Prof. T. C. Hus contributions to physical design.

An interdigitated non-contact ECG electrode for impedance compensation and signal restoration

This paper presents a non-contact electrocardiogram (ECG) measurement platform that compensates for motion-induced impedance changes via interdigitated electrode channels in concert with software reconstruction algorithms. Specifically, the impedance of the non-contact electrode is non-invasively acquired in real-time by exploiting a custom electrode designed with two independent channels featuring independent transfer functions that are used to reconstruct motion-compensated ECG waveforms. The developed platform is validated on human subjects, illustrating up to a 76.3% improvement over conventional approaches, paving the path towards comfortable, convenient, and robust non-contact electrophysiological sensing.

Impulse response generation from S-parameters for power delivery network simulation

Accurate analysis of power delivery network is indispensable to assess VLSI package and interconnection network. Given the S-parameters that characterize the linear packaging system, we derive the transient response of power delivery networks. We utilize the compressed sensing technique to generate the impulse response that fits the S-parameters with sparsity. Our method shows accurate, concise, and stable results.

Co-optimization of memory BIST grouping, test scheduling, and logic placement

Built-in self-test (BIST) is a well-known design technique in which part of a circuit is used to test the circuit itself. BIST plays an important role for embedded memories, which do not have pins or pads exposed toward the periphery of the chip for testing with automatic test equipment. With the rapidly increasing number of embedded memories in modern SOCs (up to hundreds of memories in each hard macro of the SOC), product designers incur substantial costs of test time (subject to possible power constraints) and BIST logic physical resources (area, routing, power). However, only limited previous work addresses the physical design optimization of BIST logic; notably, Chien et al. [7] optimize BIST design with respect to test time, routing length, and area. In our work, we propose a new three-step heuristic approach to minimize test time as well as test physical layout resources, subject to given upper bounds on power consumption. A key contribution is an integer linear programming ILP framework that determines optimal test time for a given cluster of memories using either one or two BIST controllers, subject to test power limits and with full comprehension of available serialization and parallelization. Our heuristic approach integrates (i) generation of a hypergraph over the memories, with test time-aware weighting of hyperedges, along with top-down, FM-style min-cut partitioning; (ii) solution of an ILP that comprehends parallel and serial testing to optimize test scheduling per BIST controller; and (iii) placement of BIST logic to minimize routing and buffering costs. When evaluated on hard macros from a recent industrial 28nm networking SOC, our heuristic solutions reduce test time estimates by up to 11.57% with strictly fewer BIST controllers per hard macro, compared to the industrial solutions.

Fast and precise routability analysis with conditional design rules

As pin accessibility encounters more challenges due to the less number of tracks, higher pin density, and more complex design rules, routability has become one bottleneck of sub-l0 nm designs. Thus, we need a new design methodology for fast turnaround in analyzing the feasibility of the layout architecture, e.g., design rules and patterns of pin assignment. In this paper, we propose a novel framework that efficiently identifies the design rule-correct routability by creating well-organized formulation. We start with a new SAT-friendly ILP formulation which satisfies conditional design rules. In the ILP-to-SAT conversion stage, we reduce the complexity of the SAT problem by utilizing a logic minimizer and further refining the SAT formula. We demonstrate that our framework performs the routability analysis within 0.24% of ILP runtime on average, while guaranteeing the precise assessment of the routability.