Ilham Hassoune

ULPFA: A New Efficient Design of a Power-Aware Full Adder

In this paper, we first propose a new structure of a hybrid full adder, namely, the branch-based logic and pass-transistor (BBL-PT) cell, which we implemented by combining branch-based logic and pass-transistor logic. Evolution of the proposed cell from its original version to an ultralow-power (ULP) cell is described. Quantitative comparisons of the optimized version, namely, the ULP full adder (ULPFA), are carried out versus the BBL-PT full adder and its counterparts in two well-known and commonly used logic styles, i.e., conventional static CMOS logic and complementary pass logic (CPL), in a 0.13-μm PD SOI CMOS with a supply voltage of 1.2 V, demonstrating power delay product (PDP) and static power performance that are more than four times better than CPL design. This could lead to tremendous benefit for multiplier application. The implementation of an 8-bit ripple carry adder based on the ULPFA is finally described, and comparisons between adders based on full adders from the prior art and our ULPFA version demonstrate that our development outperforms the static CMOS and the CPL full adders, particularly in terms of power consumption and PDP by at least a factor of two.

Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks

A new logic style called low-swing current mode logic (LSCML) is presented. It features a dynamic and differential structure and a low-swing current mode operation. The LSCML logic style may be used for hardware implementation of secure smart cards against differential power analysis (DPA) attacks but also for implementation of self-timed circuits thanks to its self-timed operation. Electrical simulations of the Khazad S-box have been carried out in 0.13 mu m PD (partially depleted) Sol CMOS technology. For comparison purpose, the Khazad S-box was implemented with the LSCML logic and two other dynamic differential logic styles previously reported. Simulation results have shown an improved reduction of the data-dependent power signature when using LSCML circuits. Indeed the LSCML based Khazad S-box has shown a power consumption standard deviation more than two times smaller than the one in DyCML and almost two times smaller than the one in DDCVSL. (c) 2006 Elsevier Ltd. All rights reserved.

Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell

A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL_PT) and its counterpart in conventional CMOS logic, was carried out in a 0.13mum PD (partially depleted) SOI CMOS for a supply voltage of 1.2V and a threshold voltage of 0.28V. Moreover, MTCMOS (multi-threshold) circuit technique was applied on the proposed full-adder to achieve a trade-off between Ultra-Low power and high performance design. Design with DTMOS (dynamic threshold) devices was also investigated with two threshold voltage values (0.28V and 0.4V) and V-dd = 0.6V.